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Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah')
-rw-r--r--src/mainboard/amd/serengeti_cheetah/romstage.c8
1 files changed, 1 insertions, 7 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index d4d3c46c0c..247e920b95 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
@@ -32,7 +29,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
-
#if 0
static void post_code(uint8_t value) {
#if 1
@@ -50,8 +46,6 @@ static void post_code(uint8_t value) {
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
-
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
@@ -142,7 +136,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
-
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -330,3 +323,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
+