summaryrefslogtreecommitdiff
path: root/src/mainboard/amd/rumba
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/amd/rumba')
-rw-r--r--src/mainboard/amd/rumba/Config.lb4
-rw-r--r--src/mainboard/amd/rumba/auto.c77
2 files changed, 66 insertions, 15 deletions
diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb
index fe63c0e7d7..7a170791af 100644
--- a/src/mainboard/amd/rumba/Config.lb
+++ b/src/mainboard/amd/rumba/Config.lb
@@ -115,8 +115,8 @@ end
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
+mainboardinit cpu/amd/model_gx2/cpu_setup.inc
+mainboardinit cpu/amd/model_gx2/gx_setup.inc
mainboardinit ./auto.inc
##
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 6ddf367bea..b15937126b 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -9,35 +9,86 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-//#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
-//#include "superio/NSC/pc97317/pc97317_early_serial.c"
-//#include "northbridge/intel/i440bx/raminit.h"
+#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
-#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-//#include "debug.c"
//#include "lib/delay.c"
-
+#include "northbridge/amd/gx2/raminit.h"
#include "northbridge/amd/gx2/raminit.c"
+#include "sdram/generic_sdram.c"
+
+static void msr_init(void)
+{
+
+ __builtin_wrmsr(0x1808, 0x22fffc02, 0x10f3bf00);
+
+ __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
+ __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
+ __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
+ __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
+ __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
+ __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
+ __builtin_wrmsr(0x10000080, 0x3, 0x0);
+
+ __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
+ __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
+ __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
+ __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
+ __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
+ __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
+
+ __builtin_wrmsr(0x400000e3, 0xf0309c10, 0x0);
+
+ __builtin_wrmsr(0xc0002001, 0x86002, 0x0);
+ __builtin_wrmsr(0x80002001, 0x86002, 0x0);
+ __builtin_wrmsr(0xa0002001, 0x86002, 0x0);
+ __builtin_wrmsr(0x50002001, 0x27, 0x0);
+ __builtin_wrmsr(0x4c002001, 0x1, 0x0);
+
+ __builtin_wrmsr(0x20000018, 0x3400, 0x10076013);
+ __builtin_wrmsr(0x20000019, 0x696332a3, 0x18000008);
+ __builtin_wrmsr(0x2000001a, 0x101, 0x0);
+
+ __builtin_wrmsr(0x2000001c, 0xff00ff, 0x0);
+ __builtin_wrmsr(0x2000001d, 0x0, 0x0);
+ __builtin_wrmsr(0x2000001f, 0x0, 0x0);
+ __builtin_wrmsr(0x20000020, 0x6, 0x0);
+
+}
+static pll_reset(void)
+{
+
+}
static void main(unsigned long bist)
{
-// pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ static const struct mem_controller memctrl [] = {
+ {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
+ };
+
+ msr_init();
+
+ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
- while (1)
- print_err("hi\n");
+
+ print_err("hi\n");
+
/* Halt if there was a built in self test failure */
- report_bist_failure(bist);
+ //report_bist_failure(bist);
- sdram_init();
+ sdram_initialize(1, memctrl);
/* Check all of memory */
+ ram_check(0x00000000, 1024*1024);
+
#if 0
ram_check(0x00000000, msr.lo);
-#endif
-#if 0
+
static const struct {
unsigned long lo, hi;
} check_addrs[] = {