diff options
Diffstat (limited to 'src/mainboard/amd/quartet')
| -rw-r--r-- | src/mainboard/amd/quartet/Config.lb | 239 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/Options.lb | 207 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/auto.c | 258 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/chip.h | 5 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/cmos.layout | 98 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/failover.c | 68 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/fakespd.c | 62 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/irq_tables.c | 38 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/mptable.c | 232 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/reset.c | 6 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/resourcemap.c | 265 |
12 files changed, 0 insertions, 1485 deletions
diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb deleted file mode 100644 index 9233460965..0000000000 --- a/src/mainboard/amd/quartet/Config.lb +++ /dev/null @@ -1,239 +0,0 @@ -## -## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The linuxBIOS bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of linuxBIOS will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up linuxBIOS, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o - -## -## Romcc output -## -makerule ./failover.E - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit linuxBIOS entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where linuxBIOS is entered) -## -if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of linuxBIOS startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu/enable_fpu.inc -mainboardinit cpu/x86/mmx/enable_mmx.inc -mainboardinit cpu/x86/sse/enable_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse/disable_sse.inc -mainboardinit cpu/x86/mmx/disable_mmx.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/amdk8/root_complex - device pci_domain 0 on - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - chip southbridge/amd/amd8111 - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 on end - device pci 1.0 on end - end - device pci 1.0 on - chip superio/nsc/pc87360 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 on end - device pci 1.6 on end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end # 8111 - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - chip northbridge/amd/amdk8 # mc1 - device pci 19.0 on end - device pci 19.0 on - chip southbridge/amd/amd8131 # amd8131_0 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8131 # amd8131_1 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - - chip northbridge/amd/amdk8 # mc2 - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - end - - chip northbridge/amd/amdk8 # mc3 - device pci 1b.0 on end - device pci 1b.0 on end - device pci 1b.0 on end - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - end - end # pci_domain 0 - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - chip cpu/amd/socket_940 - device apic 1 on end - end - chip cpu/amd/socket_940 - device apic 2 on end - end - chip cpu/amd/socket_940 - device apic 3 on end - end - end -end - diff --git a/src/mainboard/amd/quartet/Options.lb b/src/mainboard/amd/quartet/Options.lb deleted file mode 100644 index 78b3dfbd00..0000000000 --- a/src/mainboard/amd/quartet/Options.lb +++ /dev/null @@ -1,207 +0,0 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses LINUXBIOS_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CROSS_COMPILE -uses CC -uses HOSTCC -uses OBJCOPY - -uses CONFIG_USE_INIT - - -### -### Build options -### - -## -## ROM_SIZE is the size of boot ROM that this board will use. -## -default ROM_SIZE=524288 - -## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default FALLBACK_SIZE=0x40000 - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from linuxBIOS -## -default HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default HAVE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -## -## Move the default LinuxBIOS cmos range off of AMD RTC registers -## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=4 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default MAINBOARD_PART_NUMBER="QUARTET" -default MAINBOARD_VENDOR="AMD" - -### -### LinuxBIOS layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE - -## -## LinuxBIOS C code runs at this location in RAM -## -default _RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the linuxBIOS loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c deleted file mode 100644 index 4e5eb596c0..0000000000 --- a/src/mainboard/amd/quartet/auto.c +++ /dev/null @@ -1,258 +0,0 @@ -#define ASSEMBLY 1 -//#define MAXIMUM_CONSOLE_LOGLEVEL 9 -//#define DEFAULT_CONSOLE_LOGLEVEL 9 - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include <arch/cpu.h> -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "ram/ramtest.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include <cpu/amd/model_fxx_rev.h> -#include "superio/nsc/pc87360/pc87360_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" -#include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) - -static void hard_reset(void) -{ - set_bios_reset(); - /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); -} - -/* - * GPIO28 of 8111 will control H0_MEMRESET_L - * GPIO29 of 8111 will control H1_MEMRESET_L - */ -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | - (0 << 0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | - (0 << 0), SMBUS_IO_BASE + 0xc0 + 29); - } else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | - (1 << 0), SMBUS_IO_BASE + 0xc0 + 29); - } -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - /* Set memreset_high */ - outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | - (1 << 0), SMBUS_IO_BASE + 0xc0 + 28); - udelay(90); - } -} - -/* - * generate_row is specific to board implementation - * - */ - -static unsigned int generate_row(uint8_t node, uint8_t row, - uint8_t maxnodes) -{ - /* Routing Table Node i - * - * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c - * i: 0, 1, 2, 3, 4, 5, 6, 7 - * - * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [11: 8] Response Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [19:16] Broadcast route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - */ - - uint32_t ret = 0x00010101; /* default row entry */ -/* - static const unsigned int rows_2p[2][2] = { - {0x00030101, 0x00010202}, - {0x00010202, 0x00030101} - }; -*/ - - static const unsigned int rows_4p[4][4] = { - {0x00070101, 0x00010202, 0x00030404, 0x00010204}, - {0x00010202, 0x000b0101, 0x00010208, 0x00030808}, - {0x00030808, 0x00010208, 0x000b0101, 0x00010202}, - {0x00010204, 0x00030404, 0x00010202, 0x00070101} - }; - - if (!(node >= maxnodes || row >= maxnodes)) { -/* - if (maxnodes == 2) - ret = rows_2p[node][row]; - if (maxnodes == 4) -*/ - ret = rows_4p[node][row]; - } - - return ret; -} - - -#if ( FAKE_SPDROM != 1 ) -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -#define SMBUS_HUB 0x18 - unsigned device = (ctrl->channel0[0]) >> 8; - smbus_write_byte(SMBUS_HUB, 0x01, device); - smbus_write_byte(SMBUS_HUB, 0x03, 0); -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device & 0xff, address); -} -#else -#include "fakespd.c" -#endif - -// #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "northbridge/amd/amdk8/raminit.c" -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "cpu/amd/dualcore/dualcore.c" - -#include "sdram/generic_sdram.c" -/* quartet does not want the default */ -#include "resourcemap.c" - -#define RC0 ((1<<1)<<8) -#define RC1 ((1<<2)<<8) -#define RC2 ((1<<3)<<8) -#define RC3 ((1<<4)<<8) - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - -static void main(unsigned long bist) -{ - static const struct mem_controller cpu[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = {RC0 | DIMM0, RC0 | DIMM2, 0, 0}, - .channel1 = {RC0 | DIMM1, RC0 | DIMM3, 0, 0}, - }, - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = {RC1 | DIMM0, RC1 | DIMM2, 0, 0}, - .channel1 = {RC1 | DIMM1, RC1 | DIMM3, 0, 0}, - }, - { - .node_id = 2, - .f0 = PCI_DEV(0, 0x1a, 0), - .f1 = PCI_DEV(0, 0x1a, 1), - .f2 = PCI_DEV(0, 0x1a, 2), - .f3 = PCI_DEV(0, 0x1a, 3), - .channel0 = {RC2 | DIMM0, RC2 | DIMM2, 0, 0}, - .channel1 = {RC2 | DIMM1, RC2 | DIMM3, 0, 0}, - }, - { - .node_id = 3, - .f0 = PCI_DEV(0, 0x1b, 0), - .f1 = PCI_DEV(0, 0x1b, 1), - .f2 = PCI_DEV(0, 0x1b, 2), - .f3 = PCI_DEV(0, 0x1b, 3), - .channel0 = {RC3 | DIMM0, RC3 | DIMM2, 0, 0}, - .channel1 = {RC3 | DIMM1, RC3 | DIMM3, 0, 0}, - } - }; - - int needs_reset; - unsigned nodeid; - - if (bist == 0) { - k8_init_and_stop_secondaries(); - } - /* Setup the console */ - pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - setup_quartet_resource_map(); - needs_reset = setup_coherent_ht_domain(); -#if 0 - needs_reset |= ht_setup_chains(2); -#else - needs_reset |= ht_setup_chains_x(); -#endif - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } -#if 0 - print_pci_devices(); -#endif - enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif - memreset_setup(); - sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu); - -#if 0 - dump_pci_devices(); -#endif -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 2)); -#endif -#if 0 - /* Check the first 1M */ - ram_check(0x00000000, 0x000100000); -#endif -} diff --git a/src/mainboard/amd/quartet/chip.h b/src/mainboard/amd/quartet/chip.h deleted file mode 100644 index 59c2edff48..0000000000 --- a/src/mainboard/amd/quartet/chip.h +++ /dev/null @@ -1,5 +0,0 @@ -extern struct chip_operations mainboard_amd_quartet_ops; - -struct mainboard_amd_quartet_config { - int nothing; -}; diff --git a/src/mainboard/amd/quartet/cmos.layout b/src/mainboard/amd/quartet/cmos.layout deleted file mode 100644 index 5eb88b9a5a..0000000000 --- a/src/mainboard/amd/quartet/cmos.layout +++ /dev/null @@ -1,98 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 dual_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 - - diff --git a/src/mainboard/amd/quartet/failover.c b/src/mainboard/amd/quartet/failover.c deleted file mode 100644 index 1738e908d9..0000000000 --- a/src/mainboard/amd/quartet/failover.c +++ /dev/null @@ -1,68 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include "pc80/mc146818rtc_early.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" -#include "northbridge/amd/amdk8/early_ht.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "northbridge/amd/amdk8/reset_test.c" - -static unsigned long main(unsigned long bist) -{ - unsigned nodeid; - - /* Make cerain my local apic is useable */ - enable_lapic(); - - nodeid = lapicid() & 0xf; - - /* Is this a cpu only reset? */ - if (early_mtrr_init_detected()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - /* Is this a secondary cpu? */ - if (!boot_cpu()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the 8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} diff --git a/src/mainboard/amd/quartet/fakespd.c b/src/mainboard/amd/quartet/fakespd.c deleted file mode 100644 index 0bbdc59dfd..0000000000 --- a/src/mainboard/amd/quartet/fakespd.c +++ /dev/null @@ -1,62 +0,0 @@ - -#define RC0 ((1<<0)<<8) -#define RC1 ((1<<1)<<8) -#define RC2 ((1<<2)<<8) -#define RC3 ((1<<3)<<8) - -#define DIMM0 0xa0 -#define DIMM1 0xa2 -#define DIMM2 0xa4 -#define DIMM3 0xa8 - - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* dummy */ -} - - -/* - * This function is dedicated to Daniele Frijia <realcosmo@spd-online.de> - */ - -static int spd_read_byte(unsigned device, unsigned address) -{ - static const unsigned char infinion_512mb_pc2700[0x80] = { - 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, - 0x04, 0x60, 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, - 0x0e, 0x04, 0x0c, 0x01, 0x02, 0x26, 0xc0, 0x75, - 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x80, - 0x75, 0x75, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, - 0xc1, 0x49, 0x4e, 0x46, 0x49, 0x4e, 0x45, 0x4f, - 0x53, 0x37, 0x32, 0x44, 0x36, 0x34, 0x33, 0x30, - 0x30, 0x47, 0x42, 0x52, 0x36, 0x42, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x02, 0x0a, 0x03, 0x21, 0x0d, - 0x3d, 0x89, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - }; - - if (address >= 0x80) - return -1; - - /* This code is AMD quartet specific. - * DIMM0 and DIMM1 are defines of the original smbus device - * numbers on the quartet. We read them here to see which - * spd rom we should fake. - * Below construct assumes that the first two dimm sockets - * of each cpu hold a 512MB Infinion PC2700 CL2.5 ECC registered - * ddr ram module. - */ - - device &= 0xff; - if (device == DIMM0 || device == DIMM1) { - return infinion_512mb_pc2700[address]; - } - - return -1; -} diff --git a/src/mainboard/amd/quartet/irq_tables.c b/src/mainboard/amd/quartet/irq_tables.c deleted file mode 100644 index 5b9c9fabc4..0000000000 --- a/src/mainboard/amd/quartet/irq_tables.c +++ /dev/null @@ -1,38 +0,0 @@ -#include <arch/pirq_routing.h> - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*9, /* there can be total 9 devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (4<<3)|3, /* Where the interrupt router lies (dev) */ - 0x0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x746b, /* Device */ - 0, /* Crap (miniport) */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xb0, /* u8 checksum , mod 256 checksum must give zero */ - { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - /* PCI Slot 1 */ - {0x03, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x01, 0}, - /* PCI Slot 2 */ - {0x03, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x02, 0}, - /* PCI Slot 3 */ - {0x02, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x03, 0}, - /* PCI Slot 4 */ - {0x02, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x04, 0}, - /* PCI Slot 5 */ - {0x04, (0x05<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x05, 0}, - /* PCI Slot 6 */ - {0x04, (0x04<<3)|0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x06, 0}, - /* Onboard NICS */ - {0x02, (0x03<<3)|0, {{0x04, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0}, - {0x02, (0x04<<3)|0, {{0x04, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0}, - /* Let Linux know about bus 1 */ - {0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0}, - } -}; -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} diff --git a/src/mainboard/amd/quartet/mainboard.c b/src/mainboard/amd/quartet/mainboard.c deleted file mode 100644 index d3bfb13308..0000000000 --- a/src/mainboard/amd/quartet/mainboard.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - -struct chip_operations mainboard_amd_quartet_ops = { - CHIP_NAME("AMD Quartet Mainboard") -}; - diff --git a/src/mainboard/amd/quartet/mptable.c b/src/mainboard/amd/quartet/mptable.c deleted file mode 100644 index 9d3ea13127..0000000000 --- a/src/mainboard/amd/quartet/mptable.c +++ /dev/null @@ -1,232 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -void *smp_write_config_table(void *v) -{ - static const char sig[4] = "PCMP"; - static const char oem[8] = "AMD "; - static const char productid[12] = "QUARTET "; - struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - memset(mc, 0, sizeof(*mc)); - - memcpy(mc->mpc_signature, sig, sizeof(sig)); - mc->mpc_length = sizeof(*mc); /* initially just the header */ - mc->mpc_spec = 0x04; - mc->mpc_checksum = 0; /* not yet computed */ - memcpy(mc->mpc_oem, oem, sizeof(oem)); - memcpy(mc->mpc_productid, productid, sizeof(productid)); - mc->mpc_oemptr = 0; - mc->mpc_oemsize = 0; - mc->mpc_entry_count = 0; /* No entries yet... */ - mc->mpc_lapic = LAPIC_ADDR; - mc->mpe_length = 0; - mc->mpe_checksum = 0; - mc->reserved = 0; - - smp_write_processors(mc); - - { - device_t dev; - - /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } - else { - printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n"); - - bus_8111_1 = 4; - bus_isa = 5; - } - /* 8131-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n"); - - bus_8131_1 = 2; - } - /* 8131-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); - - bus_8131_2 = 3; - } - } - - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); - - /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x11, 0xfec00000); - { - device_t dev; - struct resource *res; - /* 8131 apic 3 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x03, 0x11, res->base); - } - } - /* 8131 apic 4 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x04, 0x11, res->base); - } - } - } - - /* ISA backward compatibility interrupts */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, 0x02, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x01, 0x02, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, 0x02, 0x02); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x03, 0x02, 0x03); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x04, 0x02, 0x04); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x05, 0x02, 0x05); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x06, 0x02, 0x06); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x07, 0x02, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x08, 0x02, 0x08); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x09, 0x02, 0x09); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0a, 0x02, 0x0a); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0b, 0x02, 0x0b); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0c, 0x02, 0x0c); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0d, 0x02, 0x0d); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0e, 0x02, 0x0e); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0f, 0x02, 0x0f); - - /* Standard local interrupt assignments */ - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, MP_APIC_ALL, 0x00); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, MP_APIC_ALL, 0x01); - - - /* PCI Slot 1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|3, 0x02, 0x10); - - /* PCI Slot 2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|0, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|1, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|2, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|3, 0x02, 0x11); - - /* PCI Slot 3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|3, 0x02, 0x10); - - /* PCI Slot 4 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|0, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|1, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|2, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|3, 0x02, 0x11); - - /* PCI Slot 5 */ -#warning "FIXME get the irqs right, it's just hacked to work for now" - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5<<2)|0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5<<2)|1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5<<2)|2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5<<2)|3, 0x02, 0x10); - - /* PCI Slot 6 */ -#warning "FIXME get the irqs right, it's just hacked to work for now" - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4<<2)|0, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4<<2)|1, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4<<2)|2, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4<<2)|3, 0x02, 0x13); - - /* On board nics */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (3<<2)|0, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (4<<2)|0, 0x02, 0x13); - - /* There is no extension information... */ - - /* Compute the checksums */ - mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); - mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); - printk_debug("Wrote the mp table end at: %p - %p\n", - mc, smp_next_mpe_entry(mc)); - return smp_next_mpe_entry(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr); - return (unsigned long)smp_write_config_table(v); -} - diff --git a/src/mainboard/amd/quartet/reset.c b/src/mainboard/amd/quartet/reset.c deleted file mode 100644 index 63958185f6..0000000000 --- a/src/mainboard/amd/quartet/reset.c +++ /dev/null @@ -1,6 +0,0 @@ -#include "../../../southbridge/amd/amd8111/amd8111_reset.c" - -void hard_reset(void) -{ - amd8111_hard_reset(0, 2); -} diff --git a/src/mainboard/amd/quartet/resourcemap.c b/src/mainboard/amd/quartet/resourcemap.c deleted file mode 100644 index f34e6f5327..0000000000 --- a/src/mainboard/amd/quartet/resourcemap.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * QUARTET needs a different default resource map. - * - */ - - -static void setup_quartet_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x000f0000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x001f0001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x002f0002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x003f0003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00100003, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200003, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00300003, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00ee1f20, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00f10f11, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00fbff11, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00fec020, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000b20, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00fed020, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00ec0003, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00ee2003, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00f40003, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00fec003, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00fed003, - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00002020, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00005011, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00003003, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000203, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0xff080113, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xffff0040, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0xffff0270, - }; - int max; - max = sizeof(register_values)/sizeof(register_values[0]); - setup_resource_map(register_values, max); -} - |