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-rw-r--r--src/mainboard/amd/persimmon/romstage.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 51e7a8df1f..e3ed847fdb 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -47,6 +47,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
u8 reg8;
+ // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+ __writemsr (0xc0010062, 0);
+
// early enable of SPI 33 MHz fast mode read
if (boot_cpu())
{