diff options
Diffstat (limited to 'src/mainboard/amd/persimmon/romstage.c')
| -rw-r--r-- | src/mainboard/amd/persimmon/romstage.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 749c51b649..1bcb0d1407 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -47,6 +47,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8; + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); |