aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/amd/gardenia/romstage.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/amd/gardenia/romstage.c')
-rw-r--r--src/mainboard/amd/gardenia/romstage.c94
1 files changed, 94 insertions, 0 deletions
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
new file mode 100644
index 0000000000..c3e2aa4b62
--- /dev/null
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
+#include <cpu/amd/pi/s3_resume.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+#if CONFIG_HAVE_ACPI_RESUME
+ void *resume_backup_memory;
+#endif
+
+ amd_initmmio();
+
+ hudson_lpc_port80();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+
+#if IS_ENABLED(CONFIG_HUDSON_UART)
+ configure_hudson_uart();
+#endif
+ post_code(0x31);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ AGESAWRAPPER(amdinitreset);
+ post_code(0x38);
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
+
+ post_code(0x39);
+ AGESAWRAPPER(amdinitearly);
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /* TODO: Disable cache is not ok. */
+ disable_cache_as_ram();
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ AGESAWRAPPER(amdinitresume);
+
+ AGESAWRAPPER(amds3laterestore);
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ if (s3resume || acpi_is_wakeup_s4()) {
+ outb(0xEE, PM_INDEX);
+ outb(0x8, PM_DATA);
+ }
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}