diff options
Diffstat (limited to 'src/mainboard/amd/gardenia/bootblock')
-rw-r--r-- | src/mainboard/amd/gardenia/bootblock/gpio.c (renamed from src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c) | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/gpio.c index 7e60daee27..7b18618465 100644 --- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/bootblock/gpio.c @@ -17,6 +17,22 @@ #include <amdblocks/BiosCallOuts.h> #include <soc/southbridge.h> #include <stdlib.h> +#include <soc/gpio.h> + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { + /* NFC PU */ + {GPIO_64, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, +}; + +const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { + /* BT radio disable */ + {GPIO_14, Function1, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, +}; static const GPIO_CONTROL oem_gardenia_gpio[] = { /* BT radio disable */ @@ -48,3 +64,13 @@ void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) { FchParams_reset->EarlyOemGpioTable = (void *)oem_gardenia_gpio; } + +const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size) +{ + if (GPIO_TABLE_BOOTBLOCK) { + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; + } + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} |