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-rw-r--r--src/mainboard/amd/dbm690t/Config.lb133
1 files changed, 73 insertions, 60 deletions
diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb
index b589903806..c612427ab4 100644
--- a/src/mainboard/amd/dbm690t/Config.lb
+++ b/src/mainboard/amd/dbm690t/Config.lb
@@ -54,7 +54,7 @@ default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-arch i386 end
+arch i386 end
##
## Build the objects we have code for in this directory.
@@ -65,9 +65,20 @@ driver mainboard.o
#dir /drivers/si/3114
if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE
+if HAVE_PIRQ_TABLE
object get_bus_conf.o
- object irq_tables.o
+ object irq_tables.o
+end
+
+if HAVE_ACPI_TABLES
+ object acpi_tables.o
+ object fadt.o
+ makerule dsdt.c
+ depends "$(MAINBOARD)/acpi/*.asl"
+ action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
+ action "mv dsdt.hex dsdt.c"
+ end
+ object ./dsdt.o
end
#object reset.o
@@ -78,14 +89,14 @@ if USE_DCACHE_RAM
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+ action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@"
+ action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
@@ -112,7 +123,7 @@ end
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -134,7 +145,7 @@ if USE_DCACHE_RAM
end
###
-### This is the early phase of coreboot startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
@@ -165,7 +176,7 @@ if USE_DCACHE_RAM
end
##
-## Include the secondary Configuration files
+## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
@@ -177,7 +188,7 @@ end
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
+#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
#Define gfx_dual_slot, 0: single slot, 1: dual slot
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
@@ -193,7 +204,7 @@ chip northbridge/amd/amdk8/root_complex
end
device pci_domain 0 on
chip northbridge/amd/amdk8
- device pci 18.0 on # southbridge
+ device pci 18.0 on # southbridge
chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
@@ -221,13 +232,13 @@ chip northbridge/amd/amdk8/root_complex
register "gfx_link_width" = "0"
end
chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
- device pci 12.0 on end # SATA 0x4380
- device pci 13.0 on end # USB 0x4387
- device pci 13.1 on end # USB 0x4388
- device pci 13.2 on end # USB 0x4389
- device pci 13.3 on end # USB 0x438a
- device pci 13.4 on end # USB 0x438b
- device pci 13.5 on end # USB 2 0x4386
+ device pci 12.0 on end # SATA 0x4380
+ device pci 13.0 on end # USB 0x4387
+ device pci 13.1 on end # USB 0x4388
+ device pci 13.2 on end # USB 0x4389
+ device pci 13.3 on end # USB 0x438a
+ device pci 13.4 on end # USB 0x438b
+ device pci 13.5 on end # USB 2 0x4386
device pci 14.0 on # SM 0x4385
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
@@ -242,49 +253,51 @@ chip northbridge/amd/amdk8/root_complex
device i2c 53 on end
end
end # SM
- device pci 14.1 on end # IDE 0x438c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x438d
- chip superio/ite/it8712f
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 off end # EC
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # Mouse
- irq 0x70 = 12
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.9 off # GAME
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # CIR
- end #superio/ite/it8712f
- end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # ACI 0x4382
- device pci 14.6 on end # MCI 0x438e
+ device pci 14.1 on end # IDE 0x438c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x438d
+ chip superio/ite/it8712f
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 off end # EC
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
+ end
+ device pnp 2e.8 off # MIDI
+ io 0x60 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.9 off # GAME
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8712f
+ end #LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # ACI 0x4382
+ device pci 14.6 on end # MCI 0x438e
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "hda_viddid" = "0x10ec0882"
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-26 05:18:48 +0000