1 files changed, 110 insertions, 0 deletions
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 09b850058d..b7e0aa1a48 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -39,6 +39,116 @@ chip soc/amd/sabrina
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
 
+	register "usb_phy_custom" = "1"
+	register "usb_phy" = "{
+		.Usb2PhyPort[0] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[1] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[2] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[3] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[4] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[5] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb3PhyPort[0] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.Usb3PhyPort[1] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.Usb3PhyPort[2] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
+		.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
+		.BatteryChargerEnable = 0,
+		.PhyP3CpmP4Support = 0,
+	}"
+
 	device domain 0 on
 		device ref iommu on end
 		device ref gpp_bridge_0 on end # GBE