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Diffstat (limited to 'src/mainboard/amd/bimini_fam10/romstage.c')
-rw-r--r--src/mainboard/amd/bimini_fam10/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 0c26416e75..d4397b2372 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -80,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable port80 decoding and southbridge poweron init */
sb800_lpc_port80();
- inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */
+ inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */
}
post_code(0x30);