diff options
Diffstat (limited to 'src/mainboard/agami')
| -rw-r--r-- | src/mainboard/agami/aruma/Config.lb | 336 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/Options.lb | 222 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/acpi_tables.c | 190 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/auto.c | 181 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/chip.h | 5 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/cmos.layout | 101 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/dsdt.c | 1979 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/fadt.c | 143 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/failover.c | 66 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/hyperclocking.diff | 155 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/irq_tables.c | 60 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/mainboard.c | 339 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/mptable.c | 256 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/reset.c | 6 | ||||
| -rw-r--r-- | src/mainboard/agami/aruma/resourcemap.c | 265 |
15 files changed, 4304 insertions, 0 deletions
diff --git a/src/mainboard/agami/aruma/Config.lb b/src/mainboard/agami/aruma/Config.lb new file mode 100644 index 0000000000..c9f0d86f3f --- /dev/null +++ b/src/mainboard/agami/aruma/Config.lb @@ -0,0 +1,336 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +if HAVE_ACPI_TABLES + object acpi_tables.o + object fadt.o + object dsdt.o +end +object reset.o + + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +# config for agami/aruma +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end # device pci 18.0 + device pci 18.0 on + # devices on link 1, link 1 == LDT 1 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end # 8131 + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + #chip drivers/ati/ragexl + chip drivers/pci/onboard + device pci 4.0 on end + register "rom_address" = "0xfff80000" + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x201 + io 0x62 = 0x330 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/generic/generic + #phillips pca9545 smbus mux + device i2c 70 on + # analog_devices adm1026 + chip drivers/generic/generic + device i2c 2c on end + end + end + device i2c 70 on end + device i2c 70 on end + device i2c 70 on end + end +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 54 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 55 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 56 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 57 on end +# end + end + device pci 1.5 off end + device pci 1.6 on end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end # 8111 + end # LDT1 + device pci 18.0 on end # LDT2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + + chip northbridge/amd/amdk8 + device pci 19.0 on end # LDT0 + device pci 19.0 on end # LDT1 + device pci 19.0 on # LDT2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + end # LDT2 + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + + chip northbridge/amd/amdk8 + device pci 1a.0 on end + device pci 1a.0 on end + device pci 1a.0 on # LDT2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + + end # LDT2 + device pci 1a.1 on end + device pci 1a.2 on end + device pci 1a.3 on end + end + + chip northbridge/amd/amdk8 + device pci 1b.0 on end + device pci 1b.0 on # LDT1 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + + end + device pci 1b.0 on end + device pci 1b.1 on end + device pci 1b.2 on end + device pci 1b.3 on end + end + + + end +end + diff --git a/src/mainboard/agami/aruma/Options.lb b/src/mainboard/agami/aruma/Options.lb new file mode 100644 index 0000000000..c44fcd8ea4 --- /dev/null +++ b/src/mainboard/agami/aruma/Options.lb @@ -0,0 +1,222 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses HAVE_ACPI_TABLES +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses _RAMBASE +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +uses CONFIG_USE_INIT + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=524288 + +## +## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## +#default FALLBACK_SIZE=131072 +# 256k +default FALLBACK_SIZE=0x40000 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## incoherent_ht.c does all the work. we don't want hard reset. +## +default HAVE_HARD_RESET=0 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=23 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 +default HAVE_ACPI_TABLES=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_MAX_PHYSICAL_CPUS=4 +#default ALLOW_HT_OVERCLOCKING=1 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="ARUMA" +default MAINBOARD_VENDOR="AGAMI" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x36c0 + + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a 32K heap +## +default HEAP_SIZE=0x8000 + +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +#default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +#VGA +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +### End Options.lb +end diff --git a/src/mainboard/agami/aruma/acpi_tables.c b/src/mainboard/agami/aruma/acpi_tables.c new file mode 100644 index 0000000000..3d98d505a4 --- /dev/null +++ b/src/mainboard/agami/aruma/acpi_tables.c @@ -0,0 +1,190 @@ +/* + * Agami Aruma ACPI support + * written by Stefan Reinauer <stepan@openbios.org> + * (C) 2005 Stefan Reinauer + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +extern unsigned char AmlCode[]; + +#define IO_APIC_ADDR 0xfec00000UL + +unsigned long acpi_dump_apics(unsigned long current) +{ + unsigned int gsi_base=0x18, ioapic_nr=2; + device_t dev=0; + + /* create all subtables for 4p */ + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 16); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 17); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 18); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 19); + + /* Write 8111 IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 1, + IO_APIC_ADDR, 0); + + /* Write all 8131 IOAPICs */ + while((dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev))) { + ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr); + ioapic_nr++; + } + + current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) + current, 1, 0, 2, 0 ); + + current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) + current, 1, 0, 2, 0 ); + + return current; +} + + +/* The next two tables are used by our DSDT and are freely defined + * here. This construct is used because the bus numbers containing + * the 8131 bridges may vary so that we need to pass LinuxBIOS + * knowledge into the DSDT + */ +typedef struct lnxc_busses { + u8 secondary; + u8 subordinate; +} acpi_lnxb_busses_t; + +typedef struct acpi_lnxb { + struct acpi_table_header header; + acpi_lnxb_busses_t busses[5]; +} acpi_lnxb_t; + +/* special linuxbios acpi table */ +void acpi_create_lnxb(acpi_lnxb_t *lnxb) +{ + device_t dev; + int busidx=0; + + acpi_header_t *header=&(lnxb->header); + + /* fill out header fields */ + memcpy(header->signature, "LNXB", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "LNXBIOS ", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_lnxb_t); + header->revision = 1; + + /* + * Write external 8131 bus ranges + */ + /* first skip the onboard 8131 */ + dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, 0); + dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, dev); + /* now look at the last 8131 in each chain, + * as it contains the valid bus ranges + */ + while((dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, dev)) + && busidx<5 ) { + int subu, fn, slot; + acpi_lnxb_busses_t *busses; + + if(PCI_SLOT(dev->path.u.pci.devfn)!=4) + continue; + + busses=&(lnxb->busses[busidx]); + lnxb->busses[busidx].secondary = dev->bus->secondary; + lnxb->busses[busidx].subordinate = + pci_read_config8(dev, PCI_SUBORDINATE_BUS); + + busidx++; + } + header->checksum = acpi_checksum((void *)lnxb, sizeof(acpi_lnxb_t)); +} + + + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_lnxb_t *lnxb; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16byte */ + start = ( start + 0x0f ) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk_debug("ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt,hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk_debug("ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current+=madt->header.length; + acpi_add_table(rsdt,madt); + + printk_debug("ACPI: * LNXB\n"); + lnxb=(acpi_lnxb_t *)current; + current += sizeof(acpi_facs_t); + acpi_create_lnxb(lnxb); + + printk_debug("ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + current += ((acpi_header_t *)AmlCode)->length; + memcpy((void *)dsdt,(void *)AmlCode, \ + ((acpi_header_t *)AmlCode)->length); + + /* fix up dsdt */ + ((u32 *)dsdt)[11]=((u32)lnxb)+sizeof(acpi_header_t); + + /* recalculate checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum(dsdt,dsdt->length); + printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + printk_debug("ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdt,fadt); + + printk_info("ACPI: done.\n"); + return current; +} + diff --git a/src/mainboard/agami/aruma/auto.c b/src/mainboard/agami/aruma/auto.c new file mode 100644 index 0000000000..d5a3591305 --- /dev/null +++ b/src/mainboard/agami/aruma/auto.c @@ -0,0 +1,181 @@ +#define ASSEMBLY 1 +#define ENABLE_APIC_EXT_ID 1 +#define APIC_ID_OFFSET 0x10 +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include <arch/cpu.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/cpu_rev.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" +#include "cpu/amd/dualcore/dualcore.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +static void hard_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); +} + +/* + * GPIO28 of 8111 will control H0_MEMRESET_L + * GPIO29 of 8111 will control H1_MEMRESET_L + */ +static void memreset_setup(void) +{ + if (is_cpu_pre_c0()) { + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), + SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), + SMBUS_IO_BASE + 0xc0 + 29); + } else { + /* Ensure the CPU has controll of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), + SMBUS_IO_BASE + 0xc0 + 29); + } +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), + SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); + } +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +#define SMBUS_SWITCH1 0x71 +#define SMBUS_SWITCH2 0x73 + /* Switch 1: pca 9545, Switch 2: pca 9543 */ + unsigned device = (ctrl->channel0[0]) >> 8; + /* Disable all outputs on SMBus switch 1 */ + smbus_send_byte(SMBUS_SWITCH1, 0x0); + /* Select SMBus switch 2 Channel 0/1 */ + smbus_send_byte(SMBUS_SWITCH2, device); +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" +#include "resourcemap.c" + +#define CHAN0 0x100 +#define CHAN1 0x200 + +#define NODE_RAM(x) \ + .node_id = 0+x, \ + .f0 = PCI_DEV(0, 0x18+x, 0), \ + .f1 = PCI_DEV(0, 0x18+x, 1), \ + .f2 = PCI_DEV(0, 0x18+x, 2), \ + .f3 = PCI_DEV(0, 0x18+x, 3) + +static void main(unsigned long bist) +{ + static const struct mem_controller cpu[] = { + { NODE_RAM(0), + .channel0 = { (0xa0>>1)|CHAN0, (0xa4>>1)|CHAN0, 0, 0 }, + .channel1 = { (0xa2>>1)|CHAN0, (0xa6>>1)|CHAN0, 0, 0 } + }, + { NODE_RAM(1), + .channel0 = { (0xa8>>1)|CHAN0, (0xac>>1)|CHAN0, 0, 0 }, + .channel1 = { (0xaa>>1)|CHAN0, (0xae>>1)|CHAN0, 0, 0 } + }, + { NODE_RAM(2), + .channel0 = { (0xa8>>1)|CHAN1, (0xac>>1)|CHAN1, 0, 0 }, + .channel1 = { (0xaa>>1)|CHAN1, (0xae>>1)|CHAN1, 0, 0 } + }, + { NODE_RAM(3), + .channel0 = { (0xa0>>1)|CHAN1, (0xa4>>1)|CHAN1, 0, 0 }, + .channel1 = { (0xa2>>1)|CHAN1, (0xa6>>1)|CHAN1, 0, 0 } + } + }; + + int needs_reset; + + if (bist == 0) { + k8_init_and_stop_secondaries(); + } + /* Setup the console */ + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_aruma_resource_map(); + needs_reset = setup_coherent_ht_domain(); + needs_reset=ht_setup_chains_x(); + +#if 0 + dump_pci_devices(); +#endif +#if 0 + print_pci_devices(); +#endif + +//#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0) +// if(read_option(CMOS_VSTART_amdk8_1GHz, CMOS_VLEN_amdk8_1GHz, 0)) +// { +// print_debug("AMDK8 allowed at 1GHz\r\n"); +// } else { +// print_debug("AMDK8 allowed at 800Hz only\r\n"); +// } +// if(read_option(CMOS_VSTART_amd8131_800MHz, CMOS_VLEN_amd8131_800MHz, 0)) +// { +// print_debug("AMD8131 allowed at 800MHz\r\n"); +// } else { +// print_debug("AMD8131 allowed at 600Hz only\r\n"); +// } +//#endif + if (needs_reset) { + print_info("HyperT reset -\r\n"); + soft_reset(); + } + + enable_smbus(); + + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + +#if 0 + /* Check the first 1M */ + ram_check(0x00000000, 0x000100000); +#endif +} diff --git a/src/mainboard/agami/aruma/chip.h b/src/mainboard/agami/aruma/chip.h new file mode 100644 index 0000000000..ec3254c28b --- /dev/null +++ b/src/mainboard/agami/aruma/chip.h @@ -0,0 +1,5 @@ +extern struct chip_operations mainboard_agami_aruma_ops; + +struct mainboard_agami_aruma_config { + int nothing; +}; diff --git a/src/mainboard/agami/aruma/cmos.layout b/src/mainboard/agami/aruma/cmos.layout new file mode 100644 index 0000000000..d0b05a9876 --- /dev/null +++ b/src/mainboard/agami/aruma/cmos.layout @@ -0,0 +1,101 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +# These two can be used to control link speeds. byte 56 +449 1 e 1 amdk8_1GHz +450 1 e 1 amd8131_800MHz +# +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/agami/aruma/dsdt.c b/src/mainboard/agami/aruma/dsdt.c new file mode 100644 index 0000000000..753de8a178 --- /dev/null +++ b/src/mainboard/agami/aruma/dsdt.c @@ -0,0 +1,1979 @@ +/* + * + * Intel ACPI Component Architecture + * ASL Optimizing Compiler / AML Disassembler version 20040220 [May 7 2004] + * Copyright (C) 2000 - 2004 Intel Corporation + * Supports ACPI Specification Revision 2.0c + * + * Compilation of "latest-dsdt.dsl" - Mon Feb 7 23:20:21 2005 + * + * C source code output + * + */ +unsigned char AmlCode[] = +{ + 0x44,0x53,0x44,0x54,0x5E,0x3D,0x00,0x00, + 0x01,0x89,0x4C,0x58,0x42,0x49,0x4F,0x53, + 0x4C,0x58,0x42,0x49,0x4F,0x53,0x00,0x00, + 0x17,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, + 0x20,0x02,0x04,0x20,0x5B,0x80,0x42,0x49, + 0x4F,0x53,0x00,0x0C,0x78,0x56,0x34,0x12, + 0x0A,0xFF,0x5B,0x81,0x38,0x42,0x49,0x4F, + 0x53,0x01,0x53,0x45,0x42,0x31,0x08,0x53, + 0x55,0x42,0x31,0x08,0x53,0x45,0x42,0x32, + 0x08,0x53,0x55,0x42,0x32,0x08,0x53,0x45, + 0x42,0x33,0x08,0x53,0x55,0x42,0x33,0x08, + 0x53,0x45,0x42,0x34,0x08,0x53,0x55,0x42, + 0x34,0x08,0x53,0x45,0x42,0x35,0x08,0x53, + 0x55,0x42,0x35,0x08,0x08,0x53,0x53,0x31, + 0x5F,0x01,0x08,0x53,0x53,0x32,0x5F,0x00, + 0x08,0x53,0x53,0x33,0x5F,0x00,0x08,0x53, + 0x53,0x34,0x5F,0x01,0x08,0x4D,0x47,0x31, + 0x42,0x00,0x08,0x4D,0x47,0x31,0x4C,0x00, + 0x08,0x4D,0x47,0x32,0x42,0x0C,0x00,0x00, + 0x00,0xAE,0x08,0x4D,0x47,0x32,0x4C,0x0C, + 0x00,0x00,0x00,0x52,0x08,0x4D,0x47,0x33, + 0x42,0x0C,0x00,0x00,0x00,0xB1,0x08,0x4D, + 0x47,0x33,0x4C,0x0C,0x00,0x00,0xC0,0x00, + 0x08,0x4D,0x47,0x34,0x42,0x0C,0x00,0x00, + 0xC0,0xB1,0x08,0x4D,0x47,0x34,0x4C,0x0C, + 0x00,0x00,0x80,0x02,0x08,0x4D,0x47,0x35, + 0x42,0x0C,0x00,0x00,0x40,0xB4,0x08,0x4D, + 0x47,0x35,0x4C,0x0C,0x00,0x00,0x80,0x4A, + 0x08,0x56,0x47,0x41,0x4F,0x00,0x08,0x49, + 0x4F,0x42,0x30,0x0B,0x00,0xA0,0x08,0x49, + 0x4F,0x4C,0x30,0x0B,0x00,0x10,0x08,0x49, + 0x4F,0x42,0x31,0x0B,0x00,0xB0,0x08,0x49, + 0x4F,0x4C,0x31,0x0B,0x00,0x20,0x08,0x49, + 0x4F,0x42,0x32,0x00,0x08,0x49,0x4F,0x4C, + 0x32,0x00,0x08,0x49,0x4F,0x42,0x33,0x00, + 0x08,0x49,0x4F,0x4C,0x33,0x00,0x08,0x49, + 0x4F,0x53,0x54,0x0A,0x0B,0x08,0x52,0x4F, + 0x4D,0x53,0x0C,0x00,0x00,0xF8,0xFF,0x08, + 0x53,0x50,0x49,0x4F,0x0A,0x2E,0x08,0x49, + 0x4F,0x31,0x42,0x0B,0x80,0x06,0x08,0x49, + 0x4F,0x31,0x4C,0x0A,0x80,0x08,0x50,0x4D, + 0x42,0x53,0x0B,0x00,0x50,0x08,0x50,0x4D, + 0x4C,0x4E,0x0A,0xC0,0x08,0x47,0x50,0x42, + 0x53,0x0B,0xC0,0x50,0x08,0x47,0x50,0x4C, + 0x4E,0x0A,0x20,0x08,0x53,0x4D,0x42,0x53, + 0x0B,0xE0,0x50,0x08,0x53,0x4D,0x42,0x4C, + 0x0A,0x20,0x08,0x41,0x50,0x43,0x42,0x0C, + 0x00,0x00,0xC0,0xFE,0x08,0x41,0x50,0x43, + 0x4C,0x0B,0x00,0x10,0x14,0x0F,0x52,0x52, + 0x49,0x4F,0x04,0x70,0x0D,0x52,0x52,0x49, + 0x4F,0x00,0x5B,0x31,0x14,0x0F,0x52,0x44, + 0x4D,0x41,0x03,0x70,0x0D,0x72,0x44,0x4D, + 0x41,0x00,0x5B,0x31,0x08,0x50,0x49,0x43, + 0x4D,0x00,0x14,0x48,0x04,0x5F,0x50,0x49, + 0x43,0x01,0xA0,0x09,0x68,0x70,0x0A,0xAA, + 0x44,0x42,0x47,0x38,0xA1,0x08,0x70,0x0A, + 0x55,0x44,0x42,0x47,0x38,0x5C,0x2F,0x04, + 0x5F,0x53,0x42,0x5F,0x50,0x43,0x49,0x41, + 0x47,0x4F,0x4C,0x41,0x50,0x43,0x4D,0x5F, + 0x68,0x5C,0x2F,0x04,0x5F,0x53,0x42,0x5F, + 0x50,0x43,0x49,0x41,0x47,0x4F,0x4C,0x42, + 0x50,0x43,0x4D,0x5F,0x68,0x70,0x68,0x50, + 0x49,0x43,0x4D,0x08,0x4F,0x53,0x56,0x52, + 0xFF,0x14,0x1F,0x4F,0x53,0x46,0x4C,0x00, + 0xA0,0x0D,0x92,0x93,0x4F,0x53,0x56,0x52, + 0xFF,0xA4,0x4F,0x53,0x56,0x52,0x70,0x01, + 0x4F,0x53,0x56,0x52,0xA4,0x4F,0x53,0x56, + 0x52,0x14,0x4E,0x04,0x4D,0x43,0x54,0x48, + 0x02,0xA0,0x08,0x95,0x87,0x68,0x87,0x69, + 0xA4,0x00,0x72,0x87,0x68,0x01,0x60,0x08, + 0x42,0x55,0x46,0x30,0x11,0x02,0x60,0x08, + 0x42,0x55,0x46,0x31,0x11,0x02,0x60,0x70, + 0x68,0x42,0x55,0x46,0x30,0x70,0x69,0x42, + 0x55,0x46,0x31,0xA2,0x1A,0x60,0x76,0x60, + 0xA0,0x15,0x92,0x93,0x83,0x88,0x42,0x55, + 0x46,0x30,0x60,0x00,0x83,0x88,0x42,0x55, + 0x46,0x31,0x60,0x00,0xA4,0x00,0xA4,0x01, + 0x14,0x49,0x08,0x47,0x50,0x52,0x57,0x02, + 0x08,0x50,0x52,0x57,0x50,0x12,0x04,0x02, + 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b/src/mainboard/agami/aruma/fadt.c new file mode 100644 index 0000000000..74e454d903 --- /dev/null +++ b/src/mainboard/agami/aruma/fadt.c @@ -0,0 +1,143 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org> + */ + +#include <string.h> +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ + acpi_header_t *header=&(fadt->header); + + /* Prepare the header */ + memset((void *)fadt,0,sizeof(acpi_fadt_t)); + memcpy(header->signature,"FACP",4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id,OEM_ID,6); + memcpy(header->oem_table_id,"LXBACPI ",8); + memcpy(header->asl_compiler_id,ASLC,4); + header->asl_compiler_revision=0; + + fadt->firmware_ctrl=(unsigned long)facs; + fadt->dsdt= dsdt; + fadt->res1=0x0; + // 3=Workstation,4=Enterprise Server, 7=Performance Server + fadt->preferred_pm_profile=0x03; + fadt->sci_int=9; + // disable system management mode by setting to 0: + fadt->smi_cmd = 0x502f; + fadt->acpi_enable = 0xe1; + fadt->acpi_disable = 0x1e; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + fadt->pm1a_evt_blk = 0x5000; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = 0x5004; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = 0x0000; + fadt->pm_tmr_blk = 0x5008; + fadt->gpe0_blk = 0x5020; + fadt->gpe1_blk = 0x50b0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + fadt->gpe1_blk_len = 8; + fadt->gpe1_base = 16; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; // 0x7d these have to be + fadt->mon_alrm = 0; // 0x7e added to cmos.layout + fadt->century = 0; // 0x7f to make rtc alrm work + fadt->iapc_boot_arch = 0x3; // See table 5-11 + fadt->flags = 0xa5; + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = 0x5000; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = 0x5004; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = 0x5008; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0x5020; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 64; + fadt->x_gpe1_blk.bit_offset = 16; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x50b0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/agami/aruma/failover.c b/src/mainboard/agami/aruma/failover.c new file mode 100644 index 0000000000..16a5c9a904 --- /dev/null +++ b/src/mainboard/agami/aruma/failover.c @@ -0,0 +1,66 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/mc146818rtc_early.c" +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "northbridge/amd/amdk8/reset_test.c" + +static unsigned long main(unsigned long bist) +{ + unsigned nodeid; + /* Make cerain my local apic is useable */ + enable_lapic(); + + nodeid=lapicid(); + /* Is this a cpu only reset? */ + if (early_mtrr_init_detected()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + /* Is this a secondary cpu? */ + if (!boot_cpu()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* Setup the 8111 */ + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} diff --git a/src/mainboard/agami/aruma/hyperclocking.diff b/src/mainboard/agami/aruma/hyperclocking.diff new file mode 100644 index 0000000000..d3b421e8a2 --- /dev/null +++ b/src/mainboard/agami/aruma/hyperclocking.diff @@ -0,0 +1,155 @@ +Index: src/config/Options.lb +=================================================================== +RCS file: /cvsroot/freebios/freebios2/src/config/Options.lb,v +retrieving revision 1.56 +diff -u -r1.56 Options.lb +--- src/config/Options.lb 14 Jan 2005 21:54:16 -0000 1.56 ++++ src/config/Options.lb 26 Jan 2005 09:50:04 -0000 +@@ -815,3 +815,13 @@ + export never + comment "Configure briQ with PowerPC G4" + end ++############################################### ++# Options for amd k8 ++############################################### ++define ALLOW_HT_OVERCLOCKING ++ default 0 ++ export always ++ comment "Allow K8 and AMD8131 to operate at maximum speed" ++end ++ ++ +Index: src/devices/hypertransport.c +=================================================================== +RCS file: /cvsroot/freebios/freebios2/src/devices/hypertransport.c,v +retrieving revision 1.12 +diff -u -r1.12 hypertransport.c +--- src/devices/hypertransport.c 19 Jan 2005 01:19:37 -0000 1.12 ++++ src/devices/hypertransport.c 26 Jan 2005 09:50:04 -0000 +@@ -7,6 +7,9 @@ + #include <device/hypertransport.h> + #include <part/hard_reset.h> + #include <part/fallback_boot.h> ++#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0) ++#include <pc80/mc146818rtc.h> ++#endif + + static device_t ht_scan_get_devs(device_t *old_devices) + { +@@ -29,6 +32,9 @@ + { + /* Handle bugs in valid hypertransport frequency reporting */ + unsigned freq_cap; ++#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0) ++ int on; ++#endif + + freq_cap = pci_read_config16(dev, pos); + freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ +@@ -36,7 +42,12 @@ + /* AMD 8131 Errata 48 */ + if ((dev->vendor == PCI_VENDOR_ID_AMD) && + (dev->device == PCI_DEVICE_ID_AMD_8131_PCIX)) { ++#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0) ++ on=0; get_option(&on, "amd8131_800MHz"); ++ if(!on) freq_cap &= ~(1 << HT_FREQ_800Mhz); ++#else + freq_cap &= ~(1 << HT_FREQ_800Mhz); ++#endif + } + /* AMD 8151 Errata 23 */ + if ((dev->vendor == PCI_VENDOR_ID_AMD) && +@@ -45,7 +56,12 @@ + } + /* AMD K8 Unsupported 1Ghz? */ + if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) { ++#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0) ++ on=0; get_option(&on, "amdk8_1GHz"); ++ if(!on) freq_cap &= ~(1 << HT_FREQ_1000Mhz); ++#else + freq_cap &= ~(1 << HT_FREQ_1000Mhz); ++#endif + } + return freq_cap; + } +Index: src/northbridge/amd/amdk8/coherent_ht.c +=================================================================== +RCS file: /cvsroot/freebios/freebios2/src/northbridge/amd/amdk8/coherent_ht.c,v +retrieving revision 1.40 +diff -u -r1.40 coherent_ht.c +--- src/northbridge/amd/amdk8/coherent_ht.c 7 Jan 2005 21:12:05 -0000 1.40 ++++ src/northbridge/amd/amdk8/coherent_ht.c 26 Jan 2005 09:50:04 -0000 +@@ -266,7 +266,13 @@ + + /* AMD 8131 Errata 48 */ + if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8131_PCIX << 16))) { +- freq_cap &= ~(1 << HT_FREQ_800Mhz); ++#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0) ++ if(!read_option(CMOS_VSTART_amd8131_800MHz, ++ CMOS_VLEN_amd8131_800MHz, 0)) ++ freq_cap &= ~(1 << HT_FREQ_800Mhz); ++#else ++ freq_cap &= ~(1 << HT_FREQ_800Mhz); ++#endif + } + /* AMD 8151 Errata 23 */ + if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) { +@@ -274,7 +280,13 @@ + } + /* AMD K8 Unsupported 1Ghz? */ + if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { +- freq_cap &= ~(1 << HT_FREQ_1000Mhz); ++#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0) ++ if(!read_option(CMOS_VSTART_amdk8_1GHz, ++ CMOS_VLEN_amdk8_1GHz, 0)) ++ freq_cap &= ~(1 << HT_FREQ_1000Mhz); ++#else ++ freq_cap &= ~(1 << HT_FREQ_1000Mhz); ++#endif + } + return freq_cap; + } +Index: src/northbridge/amd/amdk8/incoherent_ht.c +=================================================================== +RCS file: /cvsroot/freebios/freebios2/src/northbridge/amd/amdk8/incoherent_ht.c,v +retrieving revision 1.15 +diff -u -r1.15 incoherent_ht.c +--- src/northbridge/amd/amdk8/incoherent_ht.c 20 Jan 2005 20:41:17 -0000 1.15 ++++ src/northbridge/amd/amdk8/incoherent_ht.c 26 Jan 2005 09:50:04 -0000 +@@ -1,6 +1,7 @@ + /* + This should be done by Eric +- 2004.12 yhlu add multi ht chain dynamically support ++ 2004.12 yhlu add multi ht chain dynamically support ++ 2005.01 stepan add HT overclocking feature + */ + #include <device/pci_def.h> + #include <device/pci_ids.h> +@@ -96,7 +97,13 @@ + + /* AMD 8131 Errata 48 */ + if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8131_PCIX << 16))) { ++#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0) ++ if(!read_option(CMOS_VSTART_amd8131_800MHz, ++ CMOS_VLEN_amd8131_800MHz, 0)) ++ freq_cap &= ~(1 << HT_FREQ_800Mhz); ++#else + freq_cap &= ~(1 << HT_FREQ_800Mhz); ++#endif + } + /* AMD 8151 Errata 23 */ + if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) { +@@ -104,7 +111,13 @@ + } + /* AMD K8 Unsupported 1Ghz? */ + if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { ++#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0) ++ if(!read_option(CMOS_VSTART_amdk8_1GHz, ++ CMOS_VLEN_amdk8_1GHz, 0)) ++ freq_cap &= ~(1 << HT_FREQ_1000Mhz); ++#else + freq_cap &= ~(1 << HT_FREQ_1000Mhz); ++#endif + } + return freq_cap; + } diff --git a/src/mainboard/agami/aruma/irq_tables.c b/src/mainboard/agami/aruma/irq_tables.c new file mode 100644 index 0000000000..2ebb94f41b --- /dev/null +++ b/src/mainboard/agami/aruma/irq_tables.c @@ -0,0 +1,60 @@ +#include <arch/pirq_routing.h> +#include <device/pci.h> + +#define IRQ_ROUTER_BUS 1 +#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) +#define IRQ_ROUTER_VENDOR 0x1022 +#define IRQ_ROUTER_DEVICE 0x746b + +#define AVAILABLE_IRQS 0xdef8 +#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \ + { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \ + {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} + +/* Each IRQ_SLOT entry consists of: + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */ + IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ + IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + IRQ_ROUTER_VENDOR, /* Vendor */ + IRQ_ROUTER_DEVICE, /* Device */ + 0x00, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x6a, /* u8 checksum , mod 256 checksum must give zero */ + { /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */ + IRQ_SLOT(0, 0x01,4,0, 1,2,3,4 ), /* 8111 PCI bridge */ + IRQ_SLOT(0, 0x04,0,0, 4,0,0,0 ), /* 8111 USB */ + IRQ_SLOT(1, 0x06,1,0, 2,3,4,1 ), /* ???? was: bus A*/ + IRQ_SLOT(2, 0x07,1,0, 2,3,4,1 ), /* ???? was: bus 9*/ + IRQ_SLOT(3, 0x0a,1,0, 2,3,4,1 ), /* IBM PCI-X <-> PCI-X */ + IRQ_SLOT(4, 0x08,1,0, 2,3,4,1 ), /* IBM PCI-X <-> PCI-X */ + IRQ_SLOT(0, 0x04,4,0, 1,0,0,0 ), /* ATI Rage */ + IRQ_SLOT(0, 0x06,2,0, 3,4,0,0 ), /* ???? was: bus A */ + IRQ_SLOT(0, 0x07,2,0, 3,4,0,0 ), /* ???? was: bus 9 */ + IRQ_SLOT(0, 0x0a,2,0, 3,4,0,0 ), /* Intel 82546EB GBit */ + IRQ_SLOT(0, 0x08,2,0, 3,4,0,0 ), /* Intel 82546EB GBit */ + IRQ_SLOT(0, 0x0d,1,0, 1,0,0,0 ), /* Marvell MV88SX5080 SATA */ + IRQ_SLOT(0, 0x0d,2,0, 2,0,0,0 ), /* Marvell MV88SX5080 SATA */ + IRQ_SLOT(0, 0x0e,1,0, 1,2,3,4 ), /* Intel Memory Controller 031a */ + IRQ_SLOT(0, 0x0f,1,0, 1,0,0,0 ), /* Marvell MV88SX5080 SATA */ + IRQ_SLOT(0, 0x04,5,0, 2,0,0,0 ), /* Intel 8255 Ethernet */ + IRQ_SLOT(5, 0x10,1,0, 1,2,3,4 ), /* ???? was: bus C */ + IRQ_SLOT(0, 0x12,1,0, 1,0,0,0 ), /* Marvell MV88SX5080 SATA */ + IRQ_SLOT(0, 0x12,2,0, 2,0,0,0 ), /* Marvell MV88SX5080 SATA */ + IRQ_SLOT(0, 0x13,1,0, 1,2,3,4 ), /* Intel Memory Controller 031b */ + IRQ_SLOT(0, 0x14,1,0, 1,0,0,0 ), /* Marvell MV88SX5080 SATA */ + IRQ_SLOT(6, 0x15,1,0, 1,2,3,4 ), /* ???? was: bus 11 */ + /* Let Linux know about bus 1 */ + IRQ_SLOT(0, 1,4,3, 0,0,0,0 ), + } +}; +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/agami/aruma/mainboard.c b/src/mainboard/agami/aruma/mainboard.c new file mode 100644 index 0000000000..8670939330 --- /dev/null +++ b/src/mainboard/agami/aruma/mainboard.c @@ -0,0 +1,339 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <part/hard_reset.h> +#include <device/smbus.h> +#include <delay.h> + +#include <arch/io.h> +#include "../../../northbridge/amd/amdk8/northbridge.h" +#include "../../../northbridge/amd/amdk8/cpu_rev.c" +#include "chip.h" + +#include "pc80/mc146818rtc.h" + + +#undef DEBUG +#define DEBUG 0 +#if DEBUG +static void debug_init(device_t dev) +{ + unsigned bus; + unsigned devfn; +#if 0 + for(bus = 0; bus < 256; bus++) { + for(devfn = 0; devfn < 256; devfn++) { + int i; + dev = dev_find_slot(bus, devfn); + if (!dev) { + continue; + } + if (!dev->enabled) { + continue; + } + printk_info("%02x:%02x.%0x aka %s\n", + bus, devfn >> 3, devfn & 7, dev_path(dev)); + for(i = 0; i < 256; i++) { + if ((i & 0x0f) == 0) { + printk_info("%02x:", i); + } + printk_info(" %02x", pci_read_config8(dev, i)); + if ((i & 0x0f) == 0xf) { + printk_info("\n"); + } + } + printk_info("\n"); + } + } +#endif +#if 0 + msr_t msr; + unsigned index; + unsigned eax, ebx, ecx, edx; + index = 0x80000007; + printk_debug("calling cpuid 0x%08x\n", index); + asm volatile( + "cpuid" + : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) + : "a" (index) + ); + printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n", + index, eax, ebx, ecx, edx); + if (edx & (3 << 1)) { + index = 0xC0010042; + printk_debug("Reading msr: 0x%08x\n", index); + msr = rdmsr(index); + printk_debug("msr[0x%08x]: 0x%08x%08x\n", + index, msr.hi, msr.hi); + } +#endif +} + +static void debug_noop(device_t dummy) +{ +} + +static struct device_operations debug_operations = { + .read_resources = debug_noop, + .set_resources = debug_noop, + .enable_resources = debug_noop, + .init = debug_init, +}; + +static unsigned int scan_root_bus(device_t root, unsigned int max) +{ + struct device_path path; + device_t debug; + max = root_dev_scan_bus(root, max); + path.type = DEVICE_PATH_PNP; + path.u.pnp.port = 0; + path.u.pnp.device = 0; + debug = alloc_dev(&root->link[1], &path); + debug->ops = &debug_operations; + return max; +} +#endif + +#if 0 +static void handle_smbus_error(int value, const char *msg) +{ + if (value >= 0) { + return; + } + switch(value) { + case SMBUS_WAIT_UNTIL_READY_TIMEOUT: + printk_emerg("SMBUS wait until ready timed out - resetting..."); + hard_reset(); + break; + case SMBUS_WAIT_UNTIL_DONE_TIMEOUT: + printk_emerg("SMBUS wait until done timed out - resetting..."); + hard_reset(); + break; + default: + die(msg); + break; + } +} + +#define ADM1026_DEVICE 0x2c /* 0x2e or 0x2d */ +#define ADM1026_REG_CONFIG1 0x00 +#define CFG1_MONITOR 0x01 +#define CFG1_INT_ENABLE 0x02 +#define CFG1_INT_CLEAR 0x04 +#define CFG1_AIN8_9 0x08 +#define CFG1_THERM_HOT 0x10 +#define CFT1_DAC_AFC 0x20 +#define CFG1_PWM_AFC 0x40 +#define CFG1_RESET 0x80 +#define ADM1026_REG_CONFIG2 0x01 +#define ADM1026_REG_CONFIG3 0x07 + + + +#define BILLION 1000000000UL + +static void verify_cpu_voltage(const char *name, + device_t dev, unsigned int reg, + unsigned factor, unsigned cpu_volts, unsigned delta) +{ + unsigned nvolts_lo, nvolts_hi; + unsigned cpuvolts_hi, cpuvolts_lo; + int value; + int loops; + + loops = 1000; + do { + value = smbus_read_byte(dev, reg); + handle_smbus_error(value, "SMBUS read byte failed"); + } while ((--loops > 0) && value == 0); + /* Convert the byte value to nanoVolts. + * My accuracy is nowhere near that good but I don't + * have to round so the math is simple. + * I can only go up to about 4.2 Volts this way so my range is + * limited. + */ + nvolts_lo = ((unsigned)value * factor); + nvolts_hi = nvolts_lo + factor - 1; + /* Get the range of acceptable cpu voltage values */ + cpuvolts_lo = cpu_volts - delta; + cpuvolts_hi = cpu_volts + delta; + if ((nvolts_lo < cpuvolts_lo) || (nvolts_hi > cpuvolts_hi)) { + printk_emerg("%s at (%u.%09u-%u.%09u)Volts expected %u.%09u+/-%u.%09uVolts\n", + name, + nvolts_lo/BILLION, nvolts_lo%BILLION, + nvolts_hi/BILLION, nvolts_hi%BILLION, + cpu_volts/BILLION, cpu_volts%BILLION, + delta/BILLION, delta%BILLION); + die(""); + } + printk_info("%s at (%u.%09u-%u.%09u)Volts\n", + name, + nvolts_lo/BILLION, nvolts_lo%BILLION, + nvolts_hi/BILLION, nvolts_hi%BILLION); + +} + +static void adm1026_enable_monitoring(device_t dev) +{ + int result; + result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); + handle_smbus_error(result, "ADM1026: cannot read config1"); + + result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET); + result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result); + handle_smbus_error(result, "ADM1026: cannot write to config1"); + + result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); + handle_smbus_error(result, "ADM1026: cannot reread config1"); + if (!(result & CFG1_MONITOR)) { + die("ADM1026: monitoring would not enable"); + } +} + + +static unsigned k8_cpu_volts(void) +{ + unsigned volts = ~0; + if (is_cpu_c0()) { + volts = 1500000000; + } + if (is_cpu_b3()) { + volts = 1550000000; + } + return volts; +} + +static void verify_cpu_voltages(device_t dev) +{ + unsigned cpu_volts; + unsigned delta; +#if 0 + delta = 50000000; +#else + delta = 75000000; +#endif + cpu_volts = k8_cpu_volts(); + if (cpu_volts == ~0) { + printk_info("Required cpu voltage unknwon not checking\n"); + return; + } + /* I need to read registers 0x37 == Ain7CPU1 core 0x2d == VcppCPU0 core */ + /* CPU1 core + * The sensor has a range of 0-2.5V and reports in + * 256 distinct steps. + */ + verify_cpu_voltage("CPU1 Vcore", dev, 0x37, 9765625, + cpu_volts, delta); + /* CPU0 core + * The sensor has range of 0-3.0V and reports in + * 256 distinct steps. + */ + verify_cpu_voltage("CPU0 Vcore", dev, 0x2d, 11718750, + cpu_volts, delta); +} + +#define SMBUS_MUX 0x70 + +static void do_verify_cpu_voltages(void) +{ + device_t smbus_dev; + device_t mux, sensor; + struct device_path mux_path, sensor_path; + int result; + int mux_setting; + + /* Find the smbus controller */ + smbus_dev = dev_find_device(0x1022, 0x746b, 0); + if (!smbus_dev) { + die("SMBUS controller not found\n"); + } + + /* Find the smbus mux */ + mux_path.type = DEVICE_PATH_I2C; + mux_path.u.i2c.device = SMBUS_MUX; + mux = find_dev_path(smbus_dev, &mux_path); + if (!mux) { + die("SMBUS mux not found\n"); + } + + /* Find the adm1026 sensor */ + sensor_path.type = DEVICE_PATH_I2C; + sensor_path.u.i2c.device = ADM1026_DEVICE; + sensor = find_dev_path(mux, &sensor_path); + if (!sensor) { + die("ADM1026 not found\n"); + } + + /* Set the mux to see the temperature sensors */ + mux_setting = 1; + result = smbus_send_byte(mux, mux_setting); + handle_smbus_error(result, "SMBUS send byte failed\n"); + + result = smbus_recv_byte(mux); + handle_smbus_error(result, "SMBUS recv byte failed\n"); + if (result != mux_setting) { + printk_emerg("SMBUS mux would not set to %d\n", mux_setting); + die(""); + } + + adm1026_enable_monitoring(sensor); + + /* It takes 11.38ms to read a new voltage sensor value */ + mdelay(12); + + /* Read the cpu voltages and make certain everything looks sane */ + verify_cpu_voltages(sensor); +} +#else +#define do_verify_cpu_voltages() do {} while(0) +#endif + + +static void fixup_aruma(void) +{ + msr_t msr; + + /* bit 6 (0x40) in MSR 0xC0010015 + * disables the TLB cache flush filter + */ + msr=rdmsr(0xC0010015); + msr.lo |= 0x40; + wrmsr(0xC0010015, msr); +} + + +static void mainboard_init(device_t dev) +{ + root_dev_init(dev); + + do_verify_cpu_voltages(); + + printk_info("Initializing mainboard specific functions... "); + fixup_aruma(); + printk_info("ok\n"); +} + +static struct device_operations mainboard_operations = { + .read_resources = root_dev_read_resources, + .set_resources = root_dev_set_resources, + .enable_resources = root_dev_enable_resources, + .init = mainboard_init, +#if !DEBUG + .scan_bus = root_dev_scan_bus, +#else + .scan_bus = scan_root_bus, +#endif + .enable = 0, +}; + +static void enable_dev(struct device *dev) +{ + dev->ops = &mainboard_operations; +} +struct chip_operations mainboard_agami_aruma_ops = { + .enable_dev = enable_dev, +}; + diff --git a/src/mainboard/agami/aruma/mptable.c b/src/mainboard/agami/aruma/mptable.c new file mode 100644 index 0000000000..b598a79524 --- /dev/null +++ b/src/mainboard/agami/aruma/mptable.c @@ -0,0 +1,256 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +#define WRITE_IOAPIC(bus,device,fn,id,version) \ +do { \ + device_t dev; \ + struct resource *res; \ + dev = dev_find_slot(bus, PCI_DEVFN(device,fn)); \ + if (!dev) break; \ + res = find_resource(dev, PCI_BASE_ADDRESS_0); \ + if (!res) break; \ + smp_write_ioapic(mc, id, version, res->base); \ +} while(0); + +unsigned get_apicid_base(unsigned ioapic_num) +{ + device_t dev; + unsigned apicid_base; + + dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); + apicid_base = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; + + return apicid_base; +} + + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "AGAMI "; + static const char productid[12] = "ARUMA "; + struct mp_config_table *mc; + int i; + unsigned apicid_base; + unsigned char bus_isa; + device_t dev; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + /* Write busses */ + bus_isa=22; // ISA + for (i=0; i<bus_isa; i++) + smp_write_bus(mc, i, "PCI "); + smp_write_bus(mc, bus_isa, "ISA "); + + /* enable ext_apic_id */ +#if 1 + apicid_base = 1; +#else + apicid_base = get_apicid_base(15); + if(lapicid()>=0x10) { + apicid_base = 0; + } +#endif + + printk_info("APIC ID BASE=0x%x\n",apicid_base); + + /* I/O APICs */ + smp_write_ioapic(mc, apicid_base, 0x11, 0xfec00000); // 8111 IOAPIC + /* Write all 8131 IOAPICs */ + /* (8131: bus, dev, fn) , id, version */ + WRITE_IOAPIC(0x01,1,1, apicid_base+1, 0x11); + WRITE_IOAPIC(0x01,2,1, apicid_base+2, 0x11); + WRITE_IOAPIC(0x05,1,1, apicid_base+3, 0x11); + WRITE_IOAPIC(0x05,2,1, apicid_base+4, 0x11); + WRITE_IOAPIC(0x05,3,1, apicid_base+5, 0x11); + WRITE_IOAPIC(0x05,4,1, apicid_base+6, 0x11); + WRITE_IOAPIC(0x0c,1,1, apicid_base+7, 0x11); + WRITE_IOAPIC(0x0c,2,1, apicid_base+8, 0x11); + WRITE_IOAPIC(0x0c,3,1, apicid_base+9, 0x11); + WRITE_IOAPIC(0x0c,4,1, apicid_base+10, 0x11); + WRITE_IOAPIC(0x11,1,1, apicid_base+11, 0x11); + WRITE_IOAPIC(0x11,2,1, apicid_base+12, 0x11); + WRITE_IOAPIC(0x11,3,1, apicid_base+13, 0x11); + WRITE_IOAPIC(0x11,4,1, apicid_base+14, 0x11); + + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_base, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_base, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_base, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_base, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_base, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_base, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_base, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_base, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_base, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_base, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_base, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_base, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_base, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1f, apicid_base, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x03, apicid_base, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x10, apicid_base, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, apicid_base, 0x11); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x10, 0x5, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x11, 0x5, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x14, 0x5, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x15, 0x5, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x18, 0x5, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x19, 0x5, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xa, 0x8, 0x5, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xa, 0x9, 0x5, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x10, 0x6, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x11, 0x6, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x14, 0x6, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x15, 0x6, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x18, 0x6, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x19, 0x6, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, 0x8, 0x6, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, 0x9, 0x6, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xd, 0x4, 0x7, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xd, 0x8, 0x7, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xe, 0x4, 0x8, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xf, 0x4, 0x9, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x12, 0x4, 0xb, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x12, 0x8, 0xb, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x13, 0x4, 0xc, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x14, 0x4, 0xd, 0x0); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + + /* + MP Config Extended Table Entries: + -- + System Address Space + bus ID: 0 address type: I/O address + address base: 0x9000 + address range: 0x2000 + -- + System Address Space + bus ID: 0 address type: I/O address + address base: 0x0 + address range: 0x100 + -- + System Address Space + bus ID: 0 address type: memory address + address base: 0xa0000 + address range: 0x20000 + -- + System Address Space + bus ID: 0 address type: memory address + address base: 0xaed00000 + address range: 0x2200000 + -- + System Address Space + bus ID: 0 address type: prefetch address + address base: 0xb0f00000 + address range: 0x100000 + -- + System Address Space + bus ID: 4 address type: I/O address + address base: 0xb000 + address range: 0x2000 + -- + System Address Space + bus ID: 4 address type: memory address + address base: 0xb1000000 + address range: 0x700000 + -- + System Address Space + bus ID: 4 address type: prefetch address + address base: 0xb1700000 + address range: 0x500000 + -- + System Address Space + bus ID: 11 address type: memory address + address base: 0xb1c00000 + address range: 0x400000 + -- + System Address Space + bus ID: 11 address type: prefetch address + address base: 0xb2000000 + address range: 0x2400000 + -- + System Address Space + bus ID: 16 address type: memory address + address base: 0xb4400000 + address range: 0x400000 + -- + System Address Space + bus ID: 16 address type: prefetch address + address base: 0xb4800000 + address range: 0x4a400000 + -- + Bus Heirarchy + bus ID: 21 bus info: 0x01 parent bus ID: 0-- + Compatibility Bus Address + bus ID: 0 address modifier: add + predefined range: 0x00000000-- + Compatibility Bus Address + bus ID: 4 address modifier: subtract + predefined range: 0x00000000-- + Compatibility Bus Address + bus ID: 11 address modifier: subtract + predefined range: 0x00000000-- + Compatibility Bus Address + bus ID: 16 address modifier: subtract + predefined range: 0x00000000-- + Compatibility Bus Address + bus ID: 0 address modifier: add + predefined range: 0x00000001-- + Compatibility Bus Address + bus ID: 4 address modifier: subtract + predefined range: 0x00000001-- + Compatibility Bus Address + bus ID: 11 address modifier: subtract + predefined range: 0x00000001-- + Compatibility Bus Address + bus ID: 16 address modifier: subtract + predefined range: 0x00000001 + */ + + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} + + diff --git a/src/mainboard/agami/aruma/reset.c b/src/mainboard/agami/aruma/reset.c new file mode 100644 index 0000000000..7f58d01410 --- /dev/null +++ b/src/mainboard/agami/aruma/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 1); +} diff --git a/src/mainboard/agami/aruma/resourcemap.c b/src/mainboard/agami/aruma/resourcemap.c new file mode 100644 index 0000000000..7d193ca01e --- /dev/null +++ b/src/mainboard/agami/aruma/resourcemap.c @@ -0,0 +1,265 @@ +/* + * Agami Aruma needs a different resource map + * + */ + +static void setup_aruma_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff10, // Link 1 CPU 0 + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff010, // CPU0 LDT1 + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ + + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04000103, // CPU0 LDT1 + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x0b050213, // CPU1 LDT2 + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x100c0223, // CPU2 LDT2 + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x15110133, // CPU3 LTD1 + }; + int max; + max = sizeof(register_values)/sizeof(register_values[0]); + setup_resource_map(register_values, max); +} + |