diff options
Diffstat (limited to 'src/mainboard/advansus')
| -rw-r--r-- | src/mainboard/advansus/a785e-i/Kconfig | 4 | ||||
| -rwxr-xr-x | src/mainboard/advansus/a785e-i/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/fadt.c | 81 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/get_bus_conf.c | 7 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/mainboard.c | 24 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/mptable.c | 10 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/platform_cfg.h | 222 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/pmio.c | 53 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/pmio.h | 33 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/romstage.c | 19 |
10 files changed, 277 insertions, 178 deletions
diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 6e3a4ab528..d3d8becbc6 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -33,10 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_DEBUG_CAR select SET_FIDVID -config AMD_CIMX_SB800 - bool - default y - config MAINBOARD_DIR string default advansus/a785e-i diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index cf8ec2664c..737bb1c1eb 100755 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -1,8 +1,6 @@ #romstage-y += reset.c #FIXME romstage have include test_rest.c -romstage-y += pmio.c ramstage-y += reset.c -ramstage-y += pmio.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_AMD_AGESA),y) diff --git a/src/mainboard/advansus/a785e-i/fadt.c b/src/mainboard/advansus/a785e-i/fadt.c index 53540e7b2b..c9d36f1bd4 100644 --- a/src/mainboard/advansus/a785e-i/fadt.c +++ b/src/mainboard/advansus/a785e-i/fadt.c @@ -26,27 +26,14 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include "pmio.h" - -/*extern*/ u16 pm_base = 0x800; -/* pm_base should be set in sb acpi */ -/* pm_base should be got from bar2 of rs780. Here I compact ACPI - * registers into 32 bytes limit. - * */ - -#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */ -#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */ -#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */ -#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */ +#include "SBPLATFORM.h" void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { + u16 val; acpi_header_t *header = &(fadt->header); - pm_base &= 0xFFFF; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); @@ -70,39 +57,39 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0xe2; - pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); + val = PM1_EVT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); + val = PM1_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); + val = PM1_TMR_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); + val = GPE0_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); /* CpuControl is in \_PR.CPU0, 6 bytes */ - pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF); - pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8); - - pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ - - pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); + val = CPU_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); + val = 0; + WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); + val = ACPI_PMA_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val); + + /* AcpiDecodeEnable, When set, SB uses the contents of the + * PM registers at index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + val = BIT0 | BIT1 | BIT2 | BIT4; + WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); - pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ fadt->pm1_evt_len = 4; @@ -145,7 +132,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 1; @@ -159,7 +146,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 1; @@ -173,21 +160,21 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 2a3f70b603..5c21e09d53 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -27,6 +27,9 @@ #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> +#if CONFIG_AMD_SB_CIMX +#include <sb_cimx.h> +#endif /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. @@ -144,4 +147,8 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_sb800 = apicid_base + 0; + +#if CONFIG_AMD_SB_CIMX + sb_Late_Post(); +#endif } diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 6340d97239..ff2d39550d 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -25,8 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -//#include <southbridge/amd/sb800/sb800.h> -#include "pmio.h" +#include "SBPLATFORM.h" #include "chip.h" uint64_t uma_memory_base, uma_memory_size; @@ -39,26 +38,21 @@ void enable_int_gfx(void); /* GPIO6. */ void enable_int_gfx(void) { - u8 byte; - volatile u8 *gpio_reg; - pm_iowrite(0xEA, 0x01); /* diable the PCIB */ - /* Disable Gec */ - byte = pm_ioread(0xF6); - byte |= 1; - pm_iowrite(0xF6, byte); - /* make sure the fed80000 is accessible */ - byte = pm_ioread(0x24); - byte |= 1; - pm_iowrite(0x24, byte); +#ifdef UNUSED_CODE + RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */ + RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */ +#endif + /* make sure the Acpi MMIO(fed80000) is accessible */ + RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */ + gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ *(gpio_reg + 170) = 0x1; /* gpio_gate */ - gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */ + gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */ *(gpio_reg + 0x6) = 0x8; *(gpio_reg + 170) = 0x0; diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c index dc76b81f79..72733c667c 100644 --- a/src/mainboard/advansus/a785e-i/mptable.c +++ b/src/mainboard/advansus/a785e-i/mptable.c @@ -23,8 +23,8 @@ #include <arch/io.h> #include <string.h> #include <stdint.h> -#include "pmio.h" #include <cpu/amd/amdfam10_sysconf.h> +#include <SBPLATFORM.h> extern int bus_isa; extern u8 bus_rs780[11]; @@ -61,12 +61,8 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - - dword = 0; - dword = pm_ioread(0x34) & 0xF0; - dword |= (pm_ioread(0x35) & 0xFF) << 8; - dword |= (pm_ioread(0x36) & 0xFF) << 16; - dword |= (pm_ioread(0x37) & 0xFF) << 24; + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x11, dword); for (byte = 0x0; byte < sizeof(intr_data); byte ++) { diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h new file mode 100644 index 0000000000..11cc5040d2 --- /dev/null +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _A785E_I_CFG_H_ +#define _A785E_I_CFG_H_ + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 + #define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 + #define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 + #define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 + #define BIOS_SIZE BIOS_SIZE_8M +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE NATIVE_IDE_MODE + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +#endif diff --git a/src/mainboard/advansus/a785e-i/pmio.c b/src/mainboard/advansus/a785e-i/pmio.c deleted file mode 100644 index aa4e61eb82..0000000000 --- a/src/mainboard/advansus/a785e-i/pmio.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "pmio.h" - -static void pmio_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pmio_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM_INDEX, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - return pmio_read_index(PM_INDEX, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM2_INDEX, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - return pmio_read_index(PM2_INDEX, reg); -} diff --git a/src/mainboard/advansus/a785e-i/pmio.h b/src/mainboard/advansus/a785e-i/pmio.h deleted file mode 100644 index 78ab6e9baf..0000000000 --- a/src/mainboard/advansus/a785e-i/pmio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PMIO_H_ -#define _PMIO_H_ - -#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 -#define PM2_INDEX 0xCD0 -#define PM2_DATA 0xCD1 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 9e31779118..3a33b5fc9c 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -47,7 +47,7 @@ #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include <SbEarly.h> +#include <sb_cimx.h> #include <SBPLATFORM.h> /* SB OEM constants */ #include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c" @@ -82,21 +82,6 @@ void soft_reset(void) outb(0x06, 0x0cf9); } -//FIXME copyed from sb800 -#include <pmio.h> -static void sb800_clk_output_48Mhz(void) -{ - /* AcpiMMioDecodeEn */ - u8 reg8; - reg8 = pm_ioread(0x24); - reg8 |= 1; - reg8 &= ~(1 << 1); - pm_iowrite(0x24, reg8); - - *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ -} - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -112,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); //enable port80 decoding and southbridge poweron init - sb_poweron_init(); + sb_Poweron_Init(); } post_code(0x30); |