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Diffstat (limited to 'src/mainboard/acer/g43t-am3')
-rw-r--r--src/mainboard/acer/g43t-am3/Kconfig8
-rw-r--r--src/mainboard/acer/g43t-am3/Kconfig.name3
-rw-r--r--src/mainboard/acer/g43t-am3/variants/q45t-am/data.vbtbin0 -> 1899 bytes
-rw-r--r--src/mainboard/acer/g43t-am3/variants/q45t-am/early_init.c36
-rw-r--r--src/mainboard/acer/g43t-am3/variants/q45t-am/gpio.c112
-rw-r--r--src/mainboard/acer/g43t-am3/variants/q45t-am/include/acpi/superio.asl21
-rw-r--r--src/mainboard/acer/g43t-am3/variants/q45t-am/overridetree.cb61
7 files changed, 239 insertions, 2 deletions
diff --git a/src/mainboard/acer/g43t-am3/Kconfig b/src/mainboard/acer/g43t-am3/Kconfig
index 34d191f4d5..77ce9d4ca1 100644
--- a/src/mainboard/acer/g43t-am3/Kconfig
+++ b/src/mainboard/acer/g43t-am3/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-if BOARD_ACER_G43T_AM3
+if BOARD_ACER_G43T_AM3 || BOARD_ACER_Q45T_AM
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_ITE_IT8720F
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048 if BOARD_ACER_G43T_AM3
+ select BOARD_ROMSIZE_KB_4096 if BOARD_ACER_Q45T_AM
select PCIEXP_ASPM
select PCIEXP_CLK_PM
select HAVE_OPTION_TABLE
@@ -23,18 +24,21 @@ config BOARD_SPECIFIC_OPTIONS
config VGA_BIOS_ID
string
default "8086,2e22" if BOARD_ACER_G43T_AM3
+ default "8086,2e12" if BOARD_ACER_Q45T_AM
config MAINBOARD_DIR
default "acer/g43t-am3"
config VARIANT_DIR
default "g43t-am3" if BOARD_ACER_G43T_AM3
+ default "q45t-am" if BOARD_ACER_Q45T_AM
config MAINBOARD_PART_NUMBER
default "G43T-AM3" if BOARD_ACER_G43T_AM3
+ default "Q45T-AM" if BOARD_ACER_Q45T_AM
config OVERRIDE_DEVICETREE
string
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-endif # BOARD_ACER_G43T_AM3
+endif # BOARD_ACER_G43T_AM3 || BOARD_ACER_Q45T_AM
diff --git a/src/mainboard/acer/g43t-am3/Kconfig.name b/src/mainboard/acer/g43t-am3/Kconfig.name
index 39c5158900..5b4447d46f 100644
--- a/src/mainboard/acer/g43t-am3/Kconfig.name
+++ b/src/mainboard/acer/g43t-am3/Kconfig.name
@@ -2,3 +2,6 @@
config BOARD_ACER_G43T_AM3
bool "G43T-AM3"
+
+config BOARD_ACER_Q45T_AM
+ bool "Q45T-AM"
diff --git a/src/mainboard/acer/g43t-am3/variants/q45t-am/data.vbt b/src/mainboard/acer/g43t-am3/variants/q45t-am/data.vbt
new file mode 100644
index 0000000000..0b264c303e
--- /dev/null
+++ b/src/mainboard/acer/g43t-am3/variants/q45t-am/data.vbt
Binary files differ
diff --git a/src/mainboard/acer/g43t-am3/variants/q45t-am/early_init.c b/src/mainboard/acer/g43t-am3/variants/q45t-am/early_init.c
new file mode 100644
index 0000000000..560e3432e0
--- /dev/null
+++ b/src/mainboard/acer/g43t-am3/variants/q45t-am/early_init.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootblock_common.h>
+#include <southbridge/intel/i82801jx/i82801jx.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8720f/it8720f.h>
+
+#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO)
+#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1)
+
+void bootblock_mainboard_early_init(void)
+{
+ /* Set up GPIOs on Super I/O. */
+ ite_reg_write(GPIO_DEV, 0x25, 0x00); // GPIO set 1
+ ite_reg_write(GPIO_DEV, 0x26, 0x0c); // GPIO set 2
+ ite_reg_write(GPIO_DEV, 0x27, 0x00); // GPIO set 3
+ ite_reg_write(GPIO_DEV, 0x28, 0x40); // GPIO set 4
+ ite_reg_write(GPIO_DEV, 0x29, 0x20); // GPIO set 5
+
+ /* Enable 3VSB during Suspend-to-RAM */
+ ite_enable_3vsbsw(GPIO_DEV);
+
+ /* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */
+ ite_delay_pwrgd3(GPIO_DEV);
+
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mb_get_spd_map(u8 spd_map[4])
+{
+ spd_map[0] = 0x50;
+ spd_map[1] = 0x51;
+ spd_map[2] = 0x52;
+ spd_map[3] = 0x53;
+}
diff --git a/src/mainboard/acer/g43t-am3/variants/q45t-am/gpio.c b/src/mainboard/acer/g43t-am3/variants/q45t-am/gpio.c
new file mode 100644
index 0000000000..e344fab39f
--- /dev/null
+++ b/src/mainboard/acer/g43t-am3/variants/q45t-am/gpio.c
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio6 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+ .gpio18 = GPIO_BLINK,
+
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_NATIVE,
+ .gpio39 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio72 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ },
+
+};
diff --git a/src/mainboard/acer/g43t-am3/variants/q45t-am/include/acpi/superio.asl b/src/mainboard/acer/g43t-am3/variants/q45t-am/include/acpi/superio.asl
new file mode 100644
index 0000000000..04fc150acf
--- /dev/null
+++ b/src/mainboard/acer/g43t-am3/variants/q45t-am/include/acpi/superio.asl
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef IT8720F_SHOW_SP1
+#undef IT8720F_SHOW_SP2
+#undef IT8720F_SHOW_EC
+#undef IT8720F_SHOW_KBCK
+#undef IT8720F_SHOW_KBCM
+#undef IT8720F_SHOW_GPIO
+#undef IT8720F_SHOW_CIR
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define IT8720F_SHOW_SP1 1
+#define IT8720F_SHOW_SP2 1
+#define IT8720F_SHOW_EC 1
+#define IT8720F_SHOW_KBCK 1
+#define IT8720F_SHOW_KBCM 1
+#define IT8720F_SHOW_GPIO 1
+#define IT8720F_SHOW_CIR 1
+#include <superio/ite/it8720f/acpi/superio.asl>
diff --git a/src/mainboard/acer/g43t-am3/variants/q45t-am/overridetree.cb b/src/mainboard/acer/g43t-am3/variants/q45t-am/overridetree.cb
new file mode 100644
index 0000000000..126c1abf03
--- /dev/null
+++ b/src/mainboard/acer/g43t-am3/variants/q45t-am/overridetree.cb
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/x4x # Northbridge
+ device domain 0 on # PCI domain
+ chip southbridge/intel/i82801jx # Southbridge
+ device pci 1c.1 off end # PCIe 2
+ device pci 1f.0 on # LPC bridge
+ chip superio/ite/it8720f # Super I/O
+ device pnp 2e.0 on end # Floppy
+ device pnp 2e.1 on end # COM 1
+ device pnp 2e.2 on end # COM 2
+ device pnp 2e.3 on end # Parallel port
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x000
+ io 0x62 = 0xa20
+ io 0x64 = 0xa30
+ irq 0xc0 = 0x01 # Simple IO Set 1
+ irq 0xc1 = 0x0c # Simple IO Set 2
+ irq 0xc2 = 0x00 # Simple IO Set 3
+ irq 0xc3 = 0x00 # Simple IO Set 4
+ irq 0xc4 = 0x20 # Simple IO Set 5
+ irq 0xc8 = 0x01 # Simple IO Set 1 Output
+ irq 0xc9 = 0x0c # Simple IO Set 2 Output
+ irq 0xca = 0x00 # Simple IO Set 3 Output
+ irq 0xcb = 0x00 # Simple IO Set 4 Output
+ irq 0xcc = 0x20 # Simple IO Set 5 Output
+ irq 0xf0 = 0x00
+ irq 0xf1 = 0x00
+ irq 0xf2 = 0x00
+ irq 0xf3 = 0x00
+ irq 0xf4 = 0x00
+ irq 0xf5 = 0x00
+ irq 0xf6 = 0x00
+ irq 0xf7 = 0x00
+ irq 0xf8 = 0x12
+ irq 0xf9 = 0x02
+ irq 0xfa = 0x13
+ irq 0xfb = 0x02
+ #irq 0xfc = 0xef # VID Input
+ irq 0xfd = 0x00
+ irq 0xfe = 0x00
+ end
+ device pnp 2e.a on end # CIR
+ end
+ end
+ device pci 1f.3 on # SMBus
+ chip drivers/i2c/ck505 # IDT CV194
+ register "mask" = "{ 0xff, 0xff, 0xff, 0x00,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x00, 0xff, 0xff, 0xff,
+ 0x00, 0xff }"
+ register "regs" = "{ 0x57, 0xd9, 0xfe, 0xff,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x00, 0x25, 0x7d, 0x96,
+ 0x00, 0xbf }"
+ device i2c 69 on end
+ end
+ end
+ end
+ end
+end
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 03:43:48 +0000