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-rw-r--r--src/mainboard/51nb/x210/devicetree.cb25
1 files changed, 15 insertions, 10 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 7a77e64792..1f2fa40dee 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -30,15 +30,6 @@ chip soc/intel/skylake
register "dptf_enable" = "0"
# FSP Configuration
- register "SataSalpSupport" = "1"
-
- # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[1]" = "1"
- register "SataPortsEnable[2]" = "1"
- register "SataPortsDevSlp[0]" = "1"
- register "SataPortsDevSlp[1]" = "1"
- register "SataPortsDevSlp[2]" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SkipExtGfxScan" = "1"
@@ -106,7 +97,21 @@ chip soc/intel/skylake
end
device ref thermal on end
device ref heci1 on end
- device ref sata on end
+ device ref sata on
+ register "SataSalpSupport" = "1"
+
+ # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ }"
+ register "SataPortsDevSlp" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ }"
+ end
device ref pcie_rp3 on end
device ref pcie_rp4 on end
device ref pcie_rp9 on end