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-rw-r--r--src/include/cpu/x86/smm.h26
-rw-r--r--src/include/device/pci_def.h4
2 files changed, 30 insertions, 0 deletions
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 4ab9f213f4..d28197232a 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -5,6 +5,8 @@
#include <arch/cpu.h>
#include <commonlib/region.h>
+#include <device/pci_type.h>
+#include <device/resource.h>
#include <types.h>
#define SMM_DEFAULT_BASE 0x30000
@@ -29,6 +31,8 @@
#define APM_CNT_ELOG_GSMI 0xef
#define APM_STS 0xb3
+#define SMM_PCI_RESOURCE_STORE_NUM_RESOURCES 6
+
/* Send cmd to APM_CNT with HAVE_SMI_HANDLER checking. */
int apm_control(u8 cmd);
u8 apm_get_apmc(void);
@@ -58,6 +62,13 @@ void smm_soc_exit(void);
extern unsigned char _binary_smm_start[];
extern unsigned char _binary_smm_end[];
+struct smm_pci_resource_info {
+ pci_devfn_t pci_addr;
+ uint16_t class_device;
+ uint8_t class_prog;
+ struct resource resources[SMM_PCI_RESOURCE_STORE_NUM_RESOURCES];
+};
+
struct smm_runtime {
u32 smbase;
u32 smm_size;
@@ -66,6 +77,9 @@ struct smm_runtime {
u32 gnvs_ptr;
u32 cbmemc_size;
void *cbmemc;
+#if CONFIG(SMM_PCI_RESOURCE_STORE)
+ struct smm_pci_resource_info pci_resources[CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS];
+#endif
uintptr_t save_state_top[CONFIG_MAX_CPUS];
int smm_log_level;
} __packed;
@@ -198,4 +212,16 @@ uint32_t smm_revision(void);
On AMD systems it is sometimes configurable. */
uint16_t pm_acpi_smi_cmd_port(void);
+const volatile struct smm_pci_resource_info *smm_get_pci_resource_store(void);
+
+void smm_pci_get_stored_resources(const volatile struct smm_pci_resource_info **out_slots,
+ size_t *out_size);
+/* Weak handler function to store PCI BARs. */
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size);
+/* Helper function to fill BARs from an array of device pointers. */
+bool smm_pci_resource_store_fill_resources(struct smm_pci_resource_info *slots, size_t num_slots,
+ const struct device **devices, size_t num_devices);
+
+void smm_pci_resource_store_init(struct smm_runtime *smm_runtime);
+
#endif /* CPU_X86_SMM_H */
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 69ff79d91a..aa53909d1e 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -590,4 +590,8 @@
#define PCI_DEV2DEVFN(sdev) (((sdev)>>12) & 0xff)
#define PCI_DEV2SEGBUS(sdev) (((sdev)>>20) & 0xfff)
+/* Fields from within the device's class value. */
+#define PCI_CLASS_GET_DEVICE(c) (c >> 8)
+#define PCI_CLASS_GET_PROG(c) (c & 0xff)
+
#endif /* PCI_DEF_H */