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-rw-r--r--src/include/cpu/intel/cpu_ids.h1
-rw-r--r--src/include/device/pci_ids.h5
2 files changed, 5 insertions, 1 deletions
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index d8191331d9..bb5511f126 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -64,5 +64,6 @@
#define CPUID_METEORLAKE_A0_1 0xa06a0
#define CPUID_METEORLAKE_A0_2 0xa06a1
#define CPUID_RAPTORLAKE_P_J0 0xb06a2
+#define CPUID_RAPTORLAKE_P_Q0 0xb06a3
#endif /* CPU_INTEL_CPU_IDS_H */
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index c997da44b4..429a89bb2c 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4013,7 +4013,9 @@
#define PCI_DID_INTEL_RPL_P_GT1 0xa720
#define PCI_DID_INTEL_RPL_P_GT2 0xa7a8
#define PCI_DID_INTEL_RPL_P_GT3 0xa7a0
-
+#define PCI_DID_INTEL_RPL_P_GT4 0xa7a9
+#define PCI_DID_INTEL_RPL_P_GT5 0xa7a1
+#define PCI_DID_INTEL_RPL_P_GT6 0xa721
/* Intel Northbridge Ids */
#define PCI_DID_INTEL_APL_NB 0x5af0
@@ -4136,6 +4138,7 @@
#define PCI_DID_INTEL_MTL_P_ID_3 0x7d14
#define PCI_DID_INTEL_RPL_P_ID_1 0xa706
#define PCI_DID_INTEL_RPL_P_ID_2 0xa707
+#define PCI_DID_INTEL_RPL_P_ID_3 0xa708
/* Intel SMBUS device Ids */
#define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22