15 files changed, 7 insertions, 35 deletions
diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h
index 630252bd21..62424f14fd 100644
--- a/src/include/console/ne2k.h
+++ b/src/include/console/ne2k.h
@@ -1,5 +1,3 @@
-#ifndef _NE2K_H__
-#define _NE2K_H__
 /*
  * This file is part of the coreboot project.
  *
@@ -19,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef __ROMCC__
+#ifndef _NE2K_H__
+#define _NE2K_H__
 void ne2k_append_data(unsigned char *d, int len, unsigned int base);
 int ne2k_init(unsigned int eth_nic_base);
 void ne2k_transmit(unsigned int eth_nic_base);
-#endif
 #endif /* _NE2K_H */
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index c0467beccb..ee55c2f85e 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -511,7 +511,7 @@
 #define PMLogic_BASE		(0x9D00)
 
 
-#if !defined(__ROMCC__)  && !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLER__)
 #if defined(__PRE_RAM__)
 void cpuRegInit(void);
 void SystemPreInit(void);
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 632bfe2217..4eee1568fb 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -630,7 +630,7 @@
 #define DELAY_UPPER_DISABLE_CLK135	(1 << 23)
 #define DELAY_LOWER_STATUS_MASK		0x7C0
 
-#if !defined(__ROMCC__)  && !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLER__)
 #if defined(__PRE_RAM__)
 void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
 void SystemPreInit(void);
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index f4c4d7283b..8bfae60c1f 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -105,9 +105,7 @@ typedef struct {
 	int num_states;
 } sst_table_t;
 
-#ifndef __ROMCC__
 void speedstep_gen_pstates(sst_table_t *);
-#endif
 
 #define SPEEDSTEP_MAX_POWER_YONAH	31000
 #define SPEEDSTEP_MIN_POWER_YONAH	13100
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 54b2f5488f..d4f323208b 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -51,7 +51,6 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
 	return lapic_read(LAPIC_ID) >> 24;
 }
 
-#ifndef __ROMCC__
 #if !CONFIG_AP_IN_SIPI_WAIT
 /* If we need to go back to sipi wait, we use the long non-inlined version of
  * this function in lapic_cpu_init.c
@@ -155,6 +154,5 @@ int start_cpu(struct device *cpu);
 #endif /* !__PRE_RAM__ */
 
 int boot_cpu(void);
-#endif
 
 #endif /* CPU_X86_LAPIC_H */
diff --git a/src/include/delay.h b/src/include/delay.h
index 0333879c34..676579b6ae 100644
--- a/src/include/delay.h
+++ b/src/include/delay.h
@@ -1,8 +1,6 @@
 #ifndef DELAY_H
 #define DELAY_H
 
-#if !defined( __ROMCC__)
-
 #if CONFIG_HAVE_INIT_TIMER
 void init_timer(void);
 #else
@@ -12,6 +10,4 @@ void init_timer(void);
 void udelay(unsigned usecs);
 void mdelay(unsigned msecs);
 void delay(unsigned secs);
-
-#endif
 #endif /* DELAY_H */
diff --git a/src/include/ehci.h b/src/include/ehci.h
index 29347f9911..7ec9810f62 100644
--- a/src/include/ehci.h
+++ b/src/include/ehci.h
@@ -25,7 +25,6 @@
 
 #define EHCI_BAR_INDEX		0x10
 
-#ifndef __ROMCC__
 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 
 /* Section 2.2 Host Controller Capability Registers */
@@ -201,4 +200,3 @@ struct ehci_dbg_port {
 #define DBGP_EPADDR(dev, ep)	(((dev)<<8)|(ep))
 } __attribute__ ((packed));
 #endif
-#endif
diff --git a/src/include/ip_checksum.h b/src/include/ip_checksum.h
index de26fa06cc..a1e0ffabd1 100644
--- a/src/include/ip_checksum.h
+++ b/src/include/ip_checksum.h
@@ -1,8 +1,5 @@
 #ifndef IP_CHECKSUM_H
 #define IP_CHECKSUM_H
-
-#ifndef __ROMCC__
 unsigned long compute_ip_checksum(void *addr, unsigned long length);
 unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new);
-#endif
 #endif /* IP_CHECKSUM_H */
diff --git a/src/include/lib.h b/src/include/lib.h
index 40c76f2db0..1f71d35880 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -22,7 +22,6 @@
 #ifndef __LIB_H__
 #define __LIB_H__
 #include <stdint.h>
-#ifndef __ROMCC__ /* romcc doesn't support prototypes. */
 
 #ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */
 /* Defined in src/lib/clog2.c */
@@ -43,8 +42,10 @@ void quick_ram_check(void);
 /* Defined in src/lib/stack.c */
 int checkstack(void *top_of_stack, int core);
 
+#ifndef __PRE_RAM__ // fails in bootblock compiled with romcc
 /* currently defined by a ldscript */
 extern unsigned char _estack[];
+#endif
 
 /* Defined in romstage.c */
 #if CONFIG_CPU_AMD_GEODE_LX
@@ -53,5 +54,4 @@ void cache_as_ram_main(void);
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 #endif
 
-#endif /* __ROMCC__ */
 #endif /* __LIB_H__ */
diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h
index f8e2b489ed..f4f0dcaab0 100644
--- a/src/include/pc80/i8254.h
+++ b/src/include/pc80/i8254.h
@@ -58,7 +58,5 @@
 #define PPCB_SPKR       0x02    /* Bit 1 */
 #define PPCB_T2GATE     0x01    /* Bit 0 */
 
-#ifndef __ROMCC__
 void setup_i8254(void);
 #endif
-#endif
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index ee1473b71a..29e034838c 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -203,9 +203,7 @@ static inline int get_option(void *dest __attribute__((unused)),
 #define CMOS_POST_BANK_1_MAGIC    0x81
 #define CMOS_POST_BANK_1_OFFSET   (CMOS_POST_OFFSET + 2)
 
-#if !defined(__ROMCC__)
 void cmos_post_log(void);
-#endif
 #endif /* CONFIG_CMOS_POST */
 
 #endif /*  PC80_MC146818RTC_H */
diff --git a/src/include/reset.h b/src/include/reset.h
index 79bf6d5b20..9f117dbda1 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -1,9 +1,6 @@
 #ifndef RESET_H
 #define RESET_H
 
-#if !defined( __ROMCC__ )
-/* ROMCC can't do function prototypes... */
-
 #if CONFIG_HAVE_HARD_RESET
 void hard_reset(void);
 #else
@@ -12,4 +9,3 @@ void hard_reset(void);
 void soft_reset(void);
 
 #endif
-#endif
diff --git a/src/include/uart.h b/src/include/uart.h
index 6b8d8e844c..9601bfa7c9 100644
--- a/src/include/uart.h
+++ b/src/include/uart.h
@@ -30,7 +30,7 @@
 #include <uart8250.h>
 #endif
 
-#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART
+#if CONFIG_CONSOLE_SERIAL_UART
 unsigned char uart_rx_byte(void);
 void uart_tx_byte(unsigned char data);
 void uart_tx_flush(void);
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index d1164c586c..d42e8226e4 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -114,7 +114,6 @@
 /* Line Control Settings */
 #define UART_LCS	CONFIG_TTYS0_LCS
 
-#ifndef __ROMCC__
 #if CONFIG_CONSOLE_SERIAL8250
 unsigned char uart8250_rx_byte(unsigned base_port);
 int uart8250_can_rx_byte(unsigned base_port);
@@ -145,8 +144,6 @@ void oxford_init(void);
 #endif
 #endif
 
-#endif /* __ROMCC__ */
-
 #endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */
 
 #endif /* UART8250_H */
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 8caf361f90..c3b34377fa 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -34,7 +34,6 @@ struct ehci_debug_info {
         u8 bufidx;
 };
 
-#ifndef __ROMCC__
 void enable_usbdebug(unsigned int port);
 int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size);
 int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
@@ -47,4 +46,3 @@ void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data);
 void usbdebug_tx_flush(struct ehci_debug_info *info);
 int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info);
 #endif
-#endif