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-rw-r--r--src/include/device/dram/ddr3.h1
-rw-r--r--src/include/device/dram/ddr4.h1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 74e0ff55f1..0814990eb9 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -19,7 +19,6 @@
#include <device/dram/common.h>
#include <types.h>
-
/**
* Convenience definitions for SPD offsets
*
diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h
index f258fa9f09..d22d4bc500 100644
--- a/src/include/device/dram/ddr4.h
+++ b/src/include/device/dram/ddr4.h
@@ -21,7 +21,6 @@
#define SPD_DDR4_PART_OFF 329
#define SPD_DDR4_PART_LEN 20
-
/*
* Module type (byte 3, bits 3:0) of SPD
* This definition is specific to DDR4. DDR2/3 SPDs have a different structure.