4 files changed, 18 insertions, 9 deletions
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index f965bae8c7..6f3cbdb2c1 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -13,12 +13,14 @@
 #  define NEED_LAPIC 0
 #endif
 
-static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg)
+static inline __attribute__((always_inline)) unsigned long lapic_read(
+	unsigned long reg)
 {
 	return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg));
 }
 
-static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v)
+static inline __attribute__((always_inline)) void lapic_write(unsigned long reg,
+	unsigned long v)
 {
 	*((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v;
 }
@@ -67,7 +69,8 @@ void stop_this_cpu(void);
 
 #if !defined(__PRE_RAM__)
 
-#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), sizeof(*(ptr))))
+#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
+	sizeof(*(ptr))))
 
 struct __xchg_dummy { unsigned long a[100]; };
 #define __xg(x) ((struct __xchg_dummy *)(x))
@@ -77,7 +80,8 @@ struct __xchg_dummy { unsigned long a[100]; };
  * Note 2: xchg has side effect, so that attribute volatile is necessary,
  *	  but generally the primitive is invalid, *ptr is output argument. --ANK
  */
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+	int size)
 {
 	switch (size) {
 	case 1:
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 1175f3b1ba..8070000322 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -37,7 +37,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
 	return soc_msr_read(index);
 }
 
-static inline __attribute__((always_inline)) void wrmsr(unsigned int index, msr_t msr)
+static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
+	msr_t msr)
 {
 	soc_msr_write(index, msr);
 }
@@ -64,7 +65,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
 	return result;
 }
 
-static inline __attribute__((always_inline)) void wrmsr(unsigned int index, msr_t msr)
+static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
+	msr_t msr)
 {
 	__asm__ __volatile__ (
 		"wrmsr"
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 99715ed4e6..36b5c712d9 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -147,7 +147,8 @@ static inline unsigned int fls(unsigned int x)
 #  define CACHE_ROM_SIZE CONFIG_ROM_SIZE
 # else
 #  define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
-#  if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE))
+#  if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \
+	(2 * CONFIG_ROM_SIZE))
 #   error "CACHE_ROM_SIZE is not optimal."
 #  endif
 # endif
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 48c4c0ba01..1892119d53 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -474,8 +474,10 @@ void northbridge_smi_handler(void);
 void southbridge_smi_handler(void);
 #else
 void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
-void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
+void northbridge_smi_handler(unsigned int node,
+	smm_state_save_area_t *state_save);
+void southbridge_smi_handler(unsigned int node,
+	smm_state_save_area_t *state_save);
 #endif /* CONFIG_SMM_TSEG */
 void mainboard_smi_gpi(u32 gpi_sts);
 int  mainboard_smi_apmc(u8 data);