diff options
Diffstat (limited to 'src/include/cpu/intel')
| -rw-r--r-- | src/include/cpu/intel/l2_cache.h | 1 | ||||
| -rw-r--r-- | src/include/cpu/intel/speedstep.h | 6 | ||||
| -rw-r--r-- | src/include/cpu/intel/turbo.h | 1 |
3 files changed, 1 insertions, 7 deletions
diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 35059ff74f..1303148025 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -27,7 +27,6 @@ #ifndef __P6_L2_CACHE_H #define __P6_L2_CACHE_H -#define IA32_PLATFORM_ID 0x17 #define EBL_CR_POWERON 0x2A #define BBL_CR_D0 0x88 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 5390781304..05d83ed341 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -35,11 +35,7 @@ /* Speedstep related MSRs */ -#define IA32_PLATFORM_ID 0x017 -#define IA32_PERF_STATUS 0x198 -#define IA32_PERF_CTL 0x199 -#define MSR_THERM2_CTL 0x19D -#define IA32_MISC_ENABLES 0x1A0 +#define MSR_THERM2_CTL 0x19D #define MSR_EBC_FREQUENCY_ID 0x2c #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 58f4831d4b..0880ebb07d 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -20,7 +20,6 @@ #define CPUID_LEAF_PM 6 #define PM_CAP_TURBO_MODE (1 << 1) -#define MSR_IA32_MISC_ENABLES 0x1a0 /* Disable the Monitor Mwait FSM feature */ #define MONITOR_MWAIT_DIS_MASK 0x40000 |