diff options
Diffstat (limited to 'src/include/cpu/amd')
| -rw-r--r-- | src/include/cpu/amd/amdfam10_sysconf.h | 6 | ||||
| -rw-r--r-- | src/include/cpu/amd/gx2def.h | 103 | ||||
| -rw-r--r-- | src/include/cpu/amd/lxdef.h | 105 | ||||
| -rw-r--r-- | src/include/cpu/amd/model_fxx_rev.h | 3 | ||||
| -rw-r--r-- | src/include/cpu/amd/msr.h | 3 | ||||
| -rw-r--r-- | src/include/cpu/amd/mtrr.h | 3 | ||||
| -rw-r--r-- | src/include/cpu/amd/powernow.h | 3 |
7 files changed, 131 insertions, 95 deletions
diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h index bff65ec917..a60dae3c99 100644 --- a/src/include/cpu/amd/amdfam10_sysconf.h +++ b/src/include/cpu/amd/amdfam10_sysconf.h @@ -40,7 +40,8 @@ struct amdfam10_sysconf_t { unsigned int nodes; unsigned int ht_c_num; // we only can have 32 ht chain at most - unsigned int ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable + // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable + unsigned int ht_c_conf_bus[HC_NUMS]; unsigned int io_addr_num; unsigned int conf_io_addr[HC_NUMS]; unsigned int conf_io_addrx[HC_NUMS]; @@ -50,7 +51,8 @@ struct amdfam10_sysconf_t { unsigned int segbit; unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234 - msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5 + // quad cores all cores in one node should be the same, and p0,..p5 + msr_t msr_pstate[NODE_NUMS * 5]; unsigned int needs_update_pstate_msrs; unsigned int bsp_apicid; diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 6a40d62e4b..330da8526e 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -78,10 +78,14 @@ #define GL1_PCI 4 #define GL1_FG 5 -#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx - To get on GeodeLink one bit has to be set */ +/* 1000xxxx - To get on GeodeLink one bit has to be set */ +#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ -#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */ +/* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't + * need to be routed + */ +#define MSR_CPU (GL0_CPU << 29) #define MSR_VG (GL0_VG << 29) /* 8000xxxx */ #define MSR_GP (GL0_GP << 29) /* A000xxxx */ #define MSR_DF (GL0_DF << 29) /* C000xxxx */ @@ -293,7 +297,7 @@ #define RSTPLL_UPPER_VDIV_SHIFT 6 #define RSTPLL_UPPER_FBDIV_SHIFT 0 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 -#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) +#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 #define RSTPPL_LOWER_BYPASS_SHIFT 15 #define RSTPPL_LOWER_TST_SHIFT 11 @@ -392,15 +396,23 @@ #define MAX_COL_ADDR 17 /* more fun stuff */ -#define BM 1 /* Base Mask - map power of 2 size aligned region */ +/* Base Mask - map power of 2 size aligned region */ +#define BM 1 #define BMO 2 /* BM with an offset */ #define R 3 /* Range - 4k range minimum */ #define RO 4 /* R with offset */ -#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */ +/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */ +#define SC 5 #define BMIO 6 /* Base Mask IO */ #define SCIO 7 /* Swiss 0xCeese IO */ -#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU */ -#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU */ +/* Special marker for Shadow SC descriptors so setShadow proc is independent + * of CPU + */ +#define SC_SHADOW 8 +/* Special marker for SYSMEM R descriptors so GLIUInit proc is independent + * of CPU + */ +#define R_SYSMEM 9 #define BMO_SMM 10 /* Special marker for SMM */ #define BM_SMM 11 /* Special marker for SMM */ #define BMO_DMM 12 /* Special marker for DMM */ @@ -415,33 +427,33 @@ /* Set up desc addresses from 20 - E8 */ /* This is chip specific! */ //remove after MSRINIT is gone -#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */ -#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */ -#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */ -#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */ - -#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */ -#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */ -#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */ -#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */ - -#define GLIU0_P2D_BM_0 (MSR_GLIU0 + 0x20) /* BASE1 */ -#define GLIU0_P2D_BM_1 (MSR_GLIU0 + 0x21) /* BASE2 */ +#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */ +#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */ +#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */ +#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */ + +#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */ +#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */ +#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */ +#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */ + +#define GLIU0_P2D_BM_0 (MSR_GLIU0 + 0x20) /* BASE1 */ +#define GLIU0_P2D_BM_1 (MSR_GLIU0 + 0x21) /* BASE2 */ #define GLIU0_P2D_BM_2 (MSR_GLIU0 + 0x22) #define GLIU0_P2D_BM_3 (MSR_GLIU0 + 0x23) #define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24) #define GLIU0_P2D_BM_5 (MSR_GLIU0 + 0x25) -#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) /* SMM */ -#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) /* DMM */ +#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) /* SMM */ +#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) /* DMM */ -#define GLIU0_P2D_R_0 (MSR_GLIU0 + 0x28) /* SYSMEM */ +#define GLIU0_P2D_R_0 (MSR_GLIU0 + 0x28) /* SYSMEM */ #define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29) #define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A) #define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B) -#define GLIU0_P2D_SC_0 (MSR_GLIU0 + 0x2C) /* SHADOW */ +#define GLIU0_P2D_SC_0 (MSR_GLIU0 + 0x2C) /* SHADOW */ #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) @@ -454,28 +466,28 @@ #define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7) #define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8) -#define GLIU1_P2D_BM_0 (MSR_GLIU1 + 0x20) /* BASE1 */ -#define GLIU1_P2D_BM_1 (MSR_GLIU1 + 0x21) /* BASE2 */ +#define GLIU1_P2D_BM_0 (MSR_GLIU1 + 0x20) /* BASE1 */ +#define GLIU1_P2D_BM_1 (MSR_GLIU1 + 0x21) /* BASE2 */ #define GLIU1_P2D_BM_2 (MSR_GLIU1 + 0x22) -#define GLIU1_P2D_BM_3 (MSR_GLIU1 + 0x23) /* SMM */ -#define GLIU1_P2D_BM_4 (MSR_GLIU1 + 0x24) /* DMM */ +#define GLIU1_P2D_BM_3 (MSR_GLIU1 + 0x23) /* SMM */ +#define GLIU1_P2D_BM_4 (MSR_GLIU1 + 0x24) /* DMM */ #define GLIU1_P2D_BM_5 (MSR_GLIU1 + 0x25) #define GLIU1_P2D_BM_6 (MSR_GLIU1 + 0x26) #define GLIU1_P2D_BM_7 (MSR_GLIU1 + 0x27) #define GLIU1_P2D_BM_8 (MSR_GLIU1 + 0x28) -#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x29) /* SYSMEM */ +#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x29) /* SYSMEM */ #define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2A) #define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2B) #define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2C) -#define GLIU1_P2D_SC_0 (MSR_GLIU1 + 0x2D) /* SHADOW */ +#define GLIU1_P2D_SC_0 (MSR_GLIU1 + 0x2D) /* SHADOW */ #define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0) #define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1) #define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2) -#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) /* FooGlue F0 for FPU */ +#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) /* FooGlue F0 for FPU */ #define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4) #define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5) #define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6) @@ -483,21 +495,22 @@ #define GLIU1_IOD_SC_5 (MSR_GLIU1 + 0xE8) /* definitions that are "once you are mostly up, start VSA" type things */ -#define SMM_OFFSET 0x40400000 -#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ -#define DMM_OFFSET 0x0C0000000 -#define DMM_SIZE 128 -#define FB_OFFSET 0x41000000 -#define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */ -#define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */ -#define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */ - -#define MDD_SMBUS 0x06000 /* SMBUS IO location */ -#define MDD_GPIO 0x06100 /* GPIO & ICF IO location */ -#define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */ -#define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */ -#define ACPI_BASE 0x09C00 /* ACPI Base */ -#define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */ +#define SMM_OFFSET 0x40400000 +#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ +#define DMM_OFFSET 0x0C0000000 +#define DMM_SIZE 128 +#define FB_OFFSET 0x41000000 +#define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */ +#define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */ +#define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */ + +#define MDD_SMBUS 0x06000 /* SMBUS IO location */ +#define MDD_GPIO 0x06100 /* GPIO & ICF IO location */ +#define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */ +#define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */ +#define ACPI_BASE 0x09C00 /* ACPI Base */ +/* Power Management Logic - placed at the end of ACPI */ +#define MDD_PM 0x09D00 #define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */ #define CHIPSET_DEV_NUM 15 diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 0d41c3b660..95fa53fe1f 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -21,19 +21,20 @@ #ifndef CPU_AMD_LXDEF_H #define CPU_AMD_LXDEF_H -#define CPU_ID_1_X 0x00000560 /* Stepping ID 1.x CPUbug fix to change it to 5A0*/ -#define CPU_ID_2_0 0x000005A1 -#define CPU_ID_3_0 0x000005A2 - -#define CPU_REV_1_0 0x010 -#define CPU_REV_1_1 0x011 -#define CPU_REV_2_0 0x020 -#define CPU_REV_2_1 0x021 -#define CPU_REV_2_2 0x022 -#define CPU_REV_C_0 0x030 -#define CPU_REV_C_1 0x031 -#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/ -#define CPU_REV_C_3 0x033 +/* Stepping ID 1.x CPUbug fix to change it to 5A0*/ +#define CPU_ID_1_X 0x00000560 +#define CPU_ID_2_0 0x000005A1 +#define CPU_ID_3_0 0x000005A2 + +#define CPU_REV_1_0 0x010 +#define CPU_REV_1_1 0x011 +#define CPU_REV_2_0 0x020 +#define CPU_REV_2_1 0x021 +#define CPU_REV_2_2 0x022 +#define CPU_REV_C_0 0x030 +#define CPU_REV_C_1 0x031 +#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/ +#define CPU_REV_C_3 0x033 /* MSR routing as follows*/ @@ -59,19 +60,23 @@ #define GL1_AES 6 -#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx, To get on GeodeLink one bit has to be set */ +/* 1000xxxx, To get on GeodeLink one bit has to be set */ +#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ -#define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/ +/* 0000xxxx this is not used for BIOS since code executing on CPU doesn't + * need to be routed + */ +#define MSR_CPU (GL0_CPU << 29) #define MSR_VG (GL0_VG << 29) /* 8000xxxx */ #define MSR_GP (GL0_GP << 29) /* A000xxxx */ -#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */ -#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */ -#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */ -#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ -#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ -#define MSR_FG MSR_GLCP +#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */ +#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */ +#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */ +#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ +#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ +#define MSR_FG MSR_GLCP /*GeodeLink Interface Unit 0 (GLIU0) port0*/ @@ -168,9 +173,9 @@ #define CPU_GLD_MSR_DIAG 0x2005 #define DIAG_SEL1_MODE_SHIFT 16 -#define DIAG_SEL1_SET (1 << 31) +#define DIAG_SEL1_SET (1 << 31) #define DIAG_SEL0__MODE_SHIFT 0 -#define DIAG_SET0_SET (1 << 15) +#define DIAG_SET0_SET (1 << 15) #define CPU_PF_CONF 0x1100 #define RETURN_STACK_ENABLE_SET (1 << 4) @@ -207,13 +212,13 @@ #define IM_CONFIG_LOWER_ICD_SET (1 << 8) #define IM_CONFIG_LOWER_EBE_SET (1 << 10) #define IM_CONFIG_LOWER_ABSE_SET (1 << 11) -#define IM_CONFIG_LOWER_QWT_SET (1 << 20) +#define IM_CONFIG_LOWER_QWT_SET (1 << 20) #define CPU_IC_INDEX 0x1710 -#define CPU_IC_DATA 0x1711 -#define CPU_IC_TAG 0x1712 +#define CPU_IC_DATA 0x1711 +#define CPU_IC_TAG 0x1712 #define CPU_IC_TAG_I 0x1713 #define CPU_ITB_INDEX 0x1720 -#define CPU_ITB_LRU 0x1721 +#define CPU_ITB_LRU 0x1721 #define CPU_ITB_ENTRY 0x1722 #define CPU_ITB_ENTRY_I 0x1723 #define CPU_IM_BIST_TAG 0x1730 @@ -313,7 +318,7 @@ #define CPU_BC_MSS_ARRAY_CTL2 0x1983 #define CPU_FPU_MSR_MODE 0x1A00 -#define FPU_IE_SET (1 << 0) +#define FPU_IE_SET (1 << 0) #define CPU_FP_UROM_BIST 0x1A03 @@ -386,13 +391,15 @@ #define RSTPLL_UPPER_CPUMULT_SHIFT 1 #define RSTPLL_UPPER_CPUDIV_SHIFT 0 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 -#define RSTPLL_LOWER_SWFLAGS_MASK (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT) +#define RSTPLL_LOWER_SWFLAGS_MASK \ + (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT) #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 #define RSTPPL_LOWER_COREBYPASS_SHIFT 12 #define RSTPPL_LOWER_GLBYPASS_SHIFT 11 #define RSTPPL_LOWER_PCISPEED_SHIFT 7 #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 1 -#define RSTPLL_LOWER_BOOTSTRAP_MASK (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT) +#define RSTPLL_LOWER_BOOTSTRAP_MASK \ + (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT) #define RSTPPL_LOWER_GLLOCK_SET (1 << 25) #define RSTPPL_LOWER_CORELOCK_SET (1 << 24) @@ -489,13 +496,13 @@ #define GLPCI_ExtMSR (MSR_PCI + 0x201E) #define GLPCI_SPARE (MSR_PCI + 0x201F) -#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) -#define GLPCI_SPARE_LOWER_PPD_SET (1<<5) -#define GLPCI_SPARE_LOWER_PPC_SET (1<<4) -#define GLPCI_SPARE_LOWER_MPC_SET (1<<3) -#define GLPCI_SPARE_LOWER_MME_SET (1<<2) -#define GLPCI_SPARE_LOWER_NSE_SET (1<<1) -#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) +#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) +#define GLPCI_SPARE_LOWER_PPD_SET (1<<5) +#define GLPCI_SPARE_LOWER_PPC_SET (1<<4) +#define GLPCI_SPARE_LOWER_MPC_SET (1<<3) +#define GLPCI_SPARE_LOWER_MME_SET (1<<2) +#define GLPCI_SPARE_LOWER_NSE_SET (1<<1) +#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) @@ -522,15 +529,23 @@ #define MAX_COL_ADDR 17 /* GLIU typedefs */ -#define BM 1 /* Base Mask - map power of 2 size aligned region*/ +/* Base Mask - map power of 2 size aligned region*/ +#define BM 1 #define BMO 2 /* BM with an offset*/ #define R 3 /* Range - 4k range minimum*/ #define RO 4 /* R with offset*/ -#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/ +/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/ +#define SC 5 #define BMIO 6 /* Base Mask IO*/ #define SCIO 7 /* Swiss 0xCeese IO*/ -#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU*/ -#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU*/ +/* Special marker for Shadow SC descriptors so setShadow proc is independent + * of CPU + */ +#define SC_SHADOW 8 +/* Special marker for SYSMEM R descriptors so GLIUInit proc is independent + * of CPU + */ +#define R_SYSMEM 9 #define BMO_SMM 10 /* Special marker for SMM*/ #define BM_SMM 11 /* Special marker for SMM*/ #define BMO_DMM 12 /* Special marker for DMM*/ @@ -566,7 +581,8 @@ #define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A) #define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B) -#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/ +/* SCO should only be SC*/ +#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) @@ -612,12 +628,13 @@ #define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4) #define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5) #define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6) -#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/ +/* FooGlue F0 for FPU*/ +#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* ------------------------ */ #define SMM_OFFSET 0x80400000 /* above 2GB */ -#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ +#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ /* DRAM_TERMINATED affects how the DELAY register is set. */ #define DRAM_TERMINATED 'T' diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 210a65227e..7640f6711a 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -77,7 +77,8 @@ static inline int is_e0_later_in_bsp(int nodeid) if (nodeid == 0) return !is_cpu_pre_e0(); - // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 + // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 + // always 0 pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 2); val_old = pci_read_config32(dev, 0x80); diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 31af3e6e92..614c576d03 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -2,7 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, + * Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 8099a3d1fe..b65c23b83a 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -53,7 +53,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index) return result; } -static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index, msr_t msr) +static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index, + msr_t msr) { __asm__ __volatile__ ( "wrmsr" diff --git a/src/include/cpu/amd/powernow.h b/src/include/cpu/amd/powernow.h index 63968151b0..77df7b031e 100644 --- a/src/include/cpu/amd/powernow.h +++ b/src/include/cpu/amd/powernow.h @@ -2,7 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz> - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, + * Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by |