diff options
Diffstat (limited to 'src/ec/google/chromeec')
| -rw-r--r-- | src/ec/google/chromeec/Kconfig | 1 | ||||
| -rw-r--r-- | src/ec/google/chromeec/Makefile.inc | 5 | ||||
| -rw-r--r-- | src/ec/google/chromeec/ec.h | 3 | ||||
| -rw-r--r-- | src/ec/google/chromeec/ec_lpc.c | 9 | ||||
| -rw-r--r-- | src/ec/google/chromeec/ec_mec.c | 125 |
5 files changed, 8 insertions, 135 deletions
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 1d59f1a982..3eb2c4807c 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -56,6 +56,7 @@ config EC_GOOGLE_CHROMEEC_LPC config EC_GOOGLE_CHROMEEC_MEC depends on EC_GOOGLE_CHROMEEC_LPC def_bool n + select EC_GOOGLE_COMMON_MEC help Microchip EC variant for LPC register access. diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 4fe311defb..85e259907f 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -7,26 +7,21 @@ smm-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c bootblock-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c -bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c ramstage-y += ec.c crosec_proto.c vstore.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c smm-y += ec.c crosec_proto.c smihandler.c vstore.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c -smm-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c romstage-y += ec.c crosec_proto.c vstore.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c -romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c verstage-y += ec.c crosec_proto.c vstore.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c -verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c ramstage-$(CONFIG_VBOOT) += vboot_storage.c diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 419870c35c..1e23ae9205 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -93,9 +93,6 @@ int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); #define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0 #define MEC_EMI_RANGE_END (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE) -void mec_io_bytes(int write, u16 offset, unsigned int length, - u8 *buf, u8 *csum); - enum usb_charge_mode { USB_CHARGE_MODE_DISABLED, USB_CHARGE_MODE_CHARGE_AUTO, diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index f584630f54..c8665c9e82 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <delay.h> #include <device/pnp.h> +#include <ec/google/common/mec.h> #include <stdint.h> #include <stdlib.h> @@ -40,7 +41,9 @@ static void read_bytes(u16 port, unsigned int length, u8 *dest, u8 *csum) #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC) /* Access desired range though EMI interface */ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { - mec_io_bytes(0, port, length, dest, csum); + csum += mec_io_bytes(MEC_IO_READ, MEC_EMI_BASE, + port - MEC_EMI_RANGE_START, + dest, length); return; } #endif @@ -75,7 +78,9 @@ static void write_bytes(u16 port, unsigned int length, u8 *msg, u8 *csum) #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC) /* Access desired range though EMI interface */ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { - mec_io_bytes(1, port, length, msg, csum); + csum += mec_io_bytes(MEC_IO_WRITE, MEC_EMI_BASE, + port - MEC_EMI_RANGE_START, + msg, length); return; } #endif diff --git a/src/ec/google/chromeec/ec_mec.c b/src/ec/google/chromeec/ec_mec.c deleted file mode 100644 index f08f931b1c..0000000000 --- a/src/ec/google/chromeec/ec_mec.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include "ec.h" -#include "ec_commands.h" - -enum { - /* 8-bit access */ - ACCESS_TYPE_BYTE = 0x0, - /* 16-bit access */ - ACCESS_TYPE_WORD = 0x1, - /* 32-bit access */ - ACCESS_TYPE_LONG = 0x2, - /* - * 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the - * EC data register to be incremented. - */ - ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3, -}; - -/* EMI registers are relative to base */ -#define MEC_EMI_HOST_TO_EC (MEC_EMI_BASE + 0) -#define MEC_EMI_EC_TO_HOST (MEC_EMI_BASE + 1) -#define MEC_EMI_EC_ADDRESS_B0 (MEC_EMI_BASE + 2) -#define MEC_EMI_EC_ADDRESS_B1 (MEC_EMI_BASE + 3) -#define MEC_EMI_EC_DATA_B0 (MEC_EMI_BASE + 4) -#define MEC_EMI_EC_DATA_B1 (MEC_EMI_BASE + 5) -#define MEC_EMI_EC_DATA_B2 (MEC_EMI_BASE + 6) -#define MEC_EMI_EC_DATA_B3 (MEC_EMI_BASE + 7) - -/* - * cros_ec_lpc_mec_emi_write_address - * - * Initialize EMI read / write at a given address. - * - * @addr: Starting read / write address - * @access_mode: Type of access, typically 32-bit auto-increment - */ -static void mec_emi_write_address(u16 addr, u8 access_mode) -{ - /* Address relative to start of EMI range */ - addr -= MEC_EMI_RANGE_START; - outb((addr & 0xfc) | access_mode, MEC_EMI_EC_ADDRESS_B0); - outb((addr >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1); -} - -/* - * mec_io_bytes - Read / write bytes to MEC EMI port - * - * @write: 1 on write operation, 0 on read - * @port: Base read / write address - * @length: Number of bytes to read / write - * @buf: Destination / source buffer - * @csum: Optional parameter, sums data transferred - * - */ -void mec_io_bytes(int write, u16 port, unsigned int length, u8 *buf, u8 *csum) -{ - int i = 0; - int io_addr; - u8 access_mode, new_access_mode; - - if (length == 0) - return; - - /* - * Long access cannot be used on misaligned data since reading B0 loads - * the data register and writing B3 flushes it. - */ - if ((port & 0x3) || (length < 4)) - access_mode = ACCESS_TYPE_BYTE; - else - access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT; - - /* Initialize I/O at desired address */ - mec_emi_write_address(port, access_mode); - - /* Skip bytes in case of misaligned port */ - io_addr = MEC_EMI_EC_DATA_B0 + (port & 0x3); - while (i < length) { - while (io_addr <= MEC_EMI_EC_DATA_B3) { - if (write) - outb(buf[i], io_addr++); - else - buf[i] = inb(io_addr++); - if (csum) - *csum += buf[i]; - - port++; - /* Extra bounds check in case of misaligned length */ - if (++i == length) - return; - } - - /* - * Use long auto-increment access except for misaligned write, - * since writing B3 triggers the flush. - */ - if (length - i < 4 && write) - new_access_mode = ACCESS_TYPE_BYTE; - else - new_access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT; - if (new_access_mode != access_mode || - access_mode != ACCESS_TYPE_LONG_AUTO_INCREMENT) { - access_mode = new_access_mode; - mec_emi_write_address(port, access_mode); - } - - /* Access [B0, B3] on each loop pass */ - io_addr = MEC_EMI_EC_DATA_B0; - } -} |