diff options
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 11 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/memory_init.c | 8 |
2 files changed, 18 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index e27249ff3c..274c3e5f24 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -221,6 +221,17 @@ config FSP_USES_CB_STACK without reinitializing stack pointer. This feature is supported Icelake onwards. +config FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND + bool + help + Starting with Intel CPX there is a bug in there reference code during + the pipe init. This code synchronises the CAR between sockets in FSP-M. + This code implicitly assumes that the FSP heap is right above the + RC heap, where both of them are located at the bottom part of CAR. + Select this to have an explicit handling of the FSP StackBase to work + around this issue. This is needed on multi-socket Xeon-SP systems. + This will place the FSP heap right above the FSP-M RC heap. + config FSP_TEMP_RAM_SIZE hex help diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index f5de5c345d..c096e86dfe 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -170,7 +170,13 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, [FSP_BOOT_IN_RECOVERY_MODE] = "boot in recovery mode", }; - if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { + if (CONFIG(FSP_USES_CB_STACK) && ENV_RAMINIT + && CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND)) { + extern char _fspm_heap[]; + extern char _efspm_heap[]; + arch_upd->StackBase = (uintptr_t)_fspm_heap; + arch_upd->StackSize = (size_t)(_efspm_heap - _fspm_heap); + } else if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { arch_upd->StackBase = (uintptr_t)temp_ram; arch_upd->StackSize = sizeof(temp_ram); } else if (setup_fsp_stack_frame(arch_upd, memmap)) { |