4 files changed, 6 insertions, 16 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index eddf3462c4..4683f5e5a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2016 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,7 +23,7 @@
 #include <fsp/car.h>
 #include <fsp/util.h>
 #include <soc/intel/common/util.h>
-#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
 #include <soc/pm.h>		/* chip_power_state */
 
 struct romstage_params {
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 2ba77e34ad..e505b93a26 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2014-2015 Intel Corporation
+ * Copyright (C) 2014-2016 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,12 +16,11 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <fsp/memmap.h>
+#include <fsp/romstage.h>
 #include <fsp/util.h>
 #include <lib.h> /* hexdump */
 #include <reset.h>
 #include <soc/intel/common/mma.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
 #include <string.h>
 #include <timestamp.h>
 #include <bootmode.h>
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index b17927ab09..7466575c82 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -15,8 +15,6 @@
  */
 
 #include <stddef.h>
-#include <stdint.h>
-#include <arch/cpu.h>
 #include <arch/io.h>
 #include <arch/cbfs.h>
 #include <arch/stages.h>
@@ -28,17 +26,11 @@
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #include <elog.h>
-#include <fsp/util.h>
-#include <memory_info.h>
+#include <fsp/romstage.h>
 #include <reset.h>
 #include <romstage_handoff.h>
 #include <smbios.h>
 #include <soc/intel/common/mrc_cache.h>
-#include <soc/intel/common/util.h>
-#include <soc/pei_wrapper.h>
-#include <soc/pm.h>
-#include <soc/romstage.h>
-#include <soc/spi.h>
 #include <stage_cache.h>
 #include <timestamp.h>
 #include <tpm.h>
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index e5fd9a9d56..18a2454de6 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,7 +20,6 @@
 #include <fsp/memmap.h>
 #include <fsp/romstage.h>
 #include <fsp/stack.h>
-#include <soc/intel/common/util.h>
 #include <stdlib.h>
 
 const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;