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-rw-r--r--src/drivers/Kconfig18
-rw-r--r--src/drivers/Makefile.inc2
-rw-r--r--src/drivers/dec/21143/21143pd.c70
-rw-r--r--src/drivers/dec/21143/Makefile.inc2
-rw-r--r--src/drivers/ti/pcmcia-cardbus/Makefile.inc2
-rw-r--r--src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c91
6 files changed, 185 insertions, 0 deletions
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index d2ff5d7d9f..41899ccce1 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -23,3 +23,21 @@ config DRIVERS_SIL
help
It sets PCI class to IDE compatible native mode, allowing
SeaBIOS, FILO etc... to boot from it.
+
+config DRIVERS_TI
+ bool
+
+config DRIVERS_TI_PCI1225
+ select DRIVERS_TI
+ bool
+
+config DRIVERS_TI_PCI1420
+ select DRIVERS_TI
+ bool
+
+config DRIVERS_TI_PCI1520
+ select DRIVERS_TI
+ bool
+
+config DRIVERS_DEC_21143PD
+ bool
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index de099bb6f7..e817afc96e 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -1,3 +1,5 @@
subdirs-y += generic/debug
subdirs-y += ati/ragexl
subdirs-y += sil/3114
+subdirs-y += ti/pcmcia-cardbus
+subdirs-y += dec/21143
diff --git a/src/drivers/dec/21143/21143pd.c b/src/drivers/dec/21143/21143pd.c
new file mode 100644
index 0000000000..e318a8d8df
--- /dev/null
+++ b/src/drivers/dec/21143/21143pd.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+/**
+ * The following should be set in the mainboard-specific Kconfig file.
+ */
+#if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \
+ !defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \
+ !defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION))
+#error "you must supply these values in your mainboard-specific Kconfig file"
+#endif
+
+/* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */
+/* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */
+/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */
+
+/**
+ * This driver take the values from Kconfig and load them in the registers
+ */
+static void dec_21143pd_enable( device_t dev )
+{
+ printk( BIOS_DEBUG, "Init of DECchip 21143PD/TD Kconfig style\n");
+ // Command and Status Configuration Register (Offset 0x04)
+ pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION );
+ printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) );
+ // Cache Line Size Register (Offset 0x0C)
+ pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE );
+ printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) );
+ // Expansion ROM Base Address Register (Offset 0x30)
+ pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS );
+ printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) );
+ return;
+}
+
+static struct device_operations dec_21143pd_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = dec_21143pd_enable,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver dec_21143pd_driver __pci_driver = {
+ .ops = &dec_21143pd_ops,
+ .vendor = PCI_VENDOR_ID_DEC,
+ .device = PCI_DEVICE_ID_DEC_21142,
+};
diff --git a/src/drivers/dec/21143/Makefile.inc b/src/drivers/dec/21143/Makefile.inc
new file mode 100644
index 0000000000..dcba9cdc9b
--- /dev/null
+++ b/src/drivers/dec/21143/Makefile.inc
@@ -0,0 +1,2 @@
+driver-$(CONFIG_DRIVERS_DEC_21143PD) += 21143pd.o
+
diff --git a/src/drivers/ti/pcmcia-cardbus/Makefile.inc b/src/drivers/ti/pcmcia-cardbus/Makefile.inc
new file mode 100644
index 0000000000..4a501e1b4a
--- /dev/null
+++ b/src/drivers/ti/pcmcia-cardbus/Makefile.inc
@@ -0,0 +1,2 @@
+driver-$(CONFIG_DRIVERS_TI) += ti-pcmcia-cardbus.o
+
diff --git a/src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c b/src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c
new file mode 100644
index 0000000000..06bf63258d
--- /dev/null
+++ b/src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+
+#if ( !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) )
+#error "you must supply these values in your mainboard-specific Kconfig file"
+#endif
+
+static void ti_pci1x2y_init(struct device *dev)
+{
+ printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
+ // Command register (offset 04)
+ pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR );
+ // Cache Line Size Register (offset 0x0C)
+ pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR );
+ // CardBus latency timer register (offset 1B)
+ pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR );
+ // Bridge control register (offset 3E)
+ pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR );
+ /** Enable change sub-vendor id
+ * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */
+ pci_write_config32( dev, 0x80, 0x10 );
+ pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA );
+ // Now write the correct value for SCR
+ // System Control Register (offset 0x80)
+ pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR );
+ // Multifunction routing register
+ pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR );
+ // Set Device Control Register (0x92) accordingly
+ pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 );
+ return;
+}
+
+static struct device_operations ti_pci1x2y_ops = {
+ .read_resources = NULL, //pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = ti_pci1x2y_init,
+ .scan_bus = 0,
+};
+
+#ifdef CONFIG_DRIVERS_TI_PCI1225
+static const struct pci_driver ti_pci1225_driver __pci_driver = {
+ .ops = &ti_pci1x2y_ops,
+ .vendor = PCI_VENDOR_ID_TI,
+ .device = PCI_DEVICE_ID_TI_1225,
+};
+
+#endif
+#ifdef CONFIG_DRIVERS_TI_PCI1420
+static const struct pci_driver ti_pci1420_driver __pci_driver = {
+ .ops = &ti_pci1x2y_ops,
+ .vendor = PCI_VENDOR_ID_TI,
+ .device = PCI_DEVICE_ID_TI_1420,
+};
+#endif
+#ifdef CONFIG_DRIVERS_TI_PCI1520
+static const struct pci_driver ti_pci1520_driver __pci_driver = {
+ .ops = &ti_pci1x2y_ops,
+ .vendor = PCI_VENDOR_ID_TI,
+ .device = PCI_DEVICE_ID_TI_1420,
+};
+#endif
+
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 20:49:04 +0000