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-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/memmap.h6
-rw-r--r--src/drivers/intel/fsp1_1/stack.c2
2 files changed, 4 insertions, 4 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h
index 2ac3260908..965bce646e 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/memmap.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,11 +19,11 @@
#include <types.h>
/*
- * mmap_region_granluarity must to return a size which is a positive non-zero
+ * mmap_region_granularity must to return a size which is a positive non-zero
* integer multiple of the SMM size when SMM is in use. When not using SMM,
* this value should be set to 8 MiB.
*/
-size_t mmap_region_granluarity(void);
+size_t mmap_region_granularity(void);
/* Fills in the arguments for the entire SMM region covered by chipset
* protections. e.g. TSEG. */
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index 18a2454de6..e048229baa 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -67,7 +67,7 @@ void *setup_stack_and_mtrrs(void)
* of physical address bits.
*/
mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
- alignment = mmap_region_granluarity();
+ alignment = mmap_region_granularity();
aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size,
alignment);