5 files changed, 123 insertions, 0 deletions
diff --git a/src/drivers/generic/bayhub_lv2/Kconfig b/src/drivers/generic/bayhub_lv2/Kconfig
new file mode 100644
index 0000000000..e9f66af8ed
--- /dev/null
+++ b/src/drivers/generic/bayhub_lv2/Kconfig
@@ -0,0 +1,2 @@
+config DRIVERS_GENERIC_BAYHUB_LV2
+	bool
diff --git a/src/drivers/generic/bayhub_lv2/Makefile.inc b/src/drivers/generic/bayhub_lv2/Makefile.inc
new file mode 100644
index 0000000000..11249a9262
--- /dev/null
+++ b/src/drivers/generic/bayhub_lv2/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_GENERIC_BAYHUB_LV2) += lv2.c
diff --git a/src/drivers/generic/bayhub_lv2/chip.h b/src/drivers/generic/bayhub_lv2/chip.h
new file mode 100644
index 0000000000..aa8f3fd879
--- /dev/null
+++ b/src/drivers/generic/bayhub_lv2/chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdbool.h>
+
+/* Bayhub LV2 PCIe to SD bridge */
+struct drivers_generic_bayhub_lv2_config {
+	bool enable_power_saving;
+};
diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c
new file mode 100644
index 0000000000..9e9f0746ae
--- /dev/null
+++ b/src/drivers/generic/bayhub_lv2/lv2.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Driver for BayHub Technology LV2 PCI to SD bridge */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include "chip.h"
+#include "lv2.h"
+
+static void lv2_init(struct device *dev)
+{
+	struct drivers_generic_bayhub_lv2_config *config = dev->chip_info;
+	pci_dev_init(dev);
+
+	if (!config || !config->enable_power_saving)
+		return;
+	/*
+	 * This procedure for enabling power-saving mode is from the
+	 * BayHub BIOS Implementation Guideline document.
+	 */
+	pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_OFF | LV2_PROTECT_LOCK_OFF);
+	pci_or_config32(dev, LV2_PCR_HEX_FC, LV2_PCIE_PHY_P1_ENABLE);
+	pci_update_config32(dev, LV2_PCR_HEX_E0, LV2_PCI_PM_L1_TIMER_MASK, LV2_PCI_PM_L1_TIMER);
+	pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER);
+	pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE);
+	pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING);
+	pci_update_config32(dev, LV2_PCR_HEX_248, LV2_L1_SUBSTATE_SETTING_MASK,
+			    LV2_L1_SUBSTATE_SETTING);
+	pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK,
+			    LV2_L1_SUBSTATE_OPTIMISE);
+	pci_or_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_CLKREQ);
+	pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW);
+	pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK,
+			    LV2_DRIVER_STRENGTH);
+	pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK,
+			    LV2_RESET_DMA_DISABLE);
+	pci_update_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_L1_L0_MASK,
+			    LV2_LINK_CTRL_L1_ENABLE);
+	pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON);
+	printk(BIOS_INFO, "BayHub LV2: Power-saving enabled (link_ctrl=%#x)\n",
+			pci_read_config32(dev, LV2_LINK_CTRL));
+}
+
+static struct device_operations lv2_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.ops_pci		= &pci_dev_ops_pci,
+	.init			= lv2_init,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_O2_LV2,
+	0
+};
+
+static const struct pci_driver bayhub_lv2 __pci_driver = {
+	.ops		= &lv2_ops,
+	.vendor		= PCI_VENDOR_ID_O2,
+	.devices	= pci_device_ids,
+};
+
+struct chip_operations drivers_generic_bayhub_lv2_ops = {
+	CHIP_NAME("BayHub Technology LV2 PCIe to SD bridge")
+};
diff --git a/src/drivers/generic/bayhub_lv2/lv2.h b/src/drivers/generic/bayhub_lv2/lv2.h
new file mode 100644
index 0000000000..464fed8ac0
--- /dev/null
+++ b/src/drivers/generic/bayhub_lv2/lv2.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Driver for BayHub Technology LV2 PCIe to SD bridge */
+
+#include <types.h>
+
+enum {
+	LV2_PROTECT			= 0xD0,
+	LV2_PROTECT_LOCK_OFF		= 0,
+	LV2_PROTECT_LOCK_ON		= BIT(0),
+	LV2_PROTECT_OFF			= 0,
+	LV2_PROTECT_ON			= BIT(31),
+	LV2_PCR_HEX_FC			= 0xFC,
+	LV2_PCIE_PHY_P1_ENABLE		= BIT(25),
+	LV2_ASPM_L1_TIMER		= 0x000E0000,
+	LV2_ASPM_L1_TIMER_MASK		= 0xFFF0FFFF,
+	LV2_PCR_HEX_A8			= 0xA8,
+	LV2_LTR_ENABLE			= BIT(10),
+	LV2_PCR_HEX_E0			= 0xE0,
+	LV2_PCI_PM_L1_TIMER		= 0x30000000,
+	LV2_PCI_PM_L1_TIMER_MASK	= 0x0FFFFFFF,
+	LV2_PCR_HEX_234			= 0x234,
+	LV2_MAX_LATENCY_SETTING		= 0x10011001,
+	LV2_PCR_HEX_248			= 0x248,
+	LV2_L1_SUBSTATE_SETTING		= 0x0000000A,
+	LV2_L1_SUBSTATE_SETTING_MASK	= 0xFFFFFFF0,
+	LV2_PCR_HEX_3F4			= 0x3F4,
+	LV2_L1_SUBSTATE_OPTIMISE	= 0x0000000A,
+	LV2_L1_SUBSTATE_OPTIMISE_MASK	= 0xFFFFFFF0,
+	LV2_PCR_HEX_300			= 0x300,
+	LV2_TUNING_WINDOW		= 0x00006055,
+	LV2_TUNING_WINDOW_MASK		= 0xFFFF0F00,
+	LV2_PCR_HEX_304			= 0x304,
+	LV2_DRIVER_STRENGTH		= 0x0000224B,
+	LV2_DRIVER_STRENGTH_MASK	= 0xFFFF0000,
+	LV2_PCR_HEX_308			= 0x308,
+	LV2_RESET_DMA_DISABLE		= 0x00C00000,
+	LV2_RESET_DMA_DISABLE_MASK	= 0xFF3FFFFF,
+	LV2_LINK_CTRL			= 0x90,
+	LV2_LINK_CTRL_L1_ENABLE		= BIT(1),
+	LV2_LINK_CTRL_L1_L0_MASK	= 0xFFFFFFFC,
+	LV2_LINK_CTRL_CLKREQ		= BIT(8),
+};