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-rw-r--r--src/drivers/Kconfig1
-rw-r--r--src/drivers/Makefile.inc1
-rw-r--r--src/drivers/oxford/Kconfig1
-rw-r--r--src/drivers/oxford/Makefile.inc1
-rw-r--r--src/drivers/oxford/oxpcie/Kconfig68
-rw-r--r--src/drivers/oxford/oxpcie/Makefile.inc3
-rw-r--r--src/drivers/oxford/oxpcie/oxpcie.c56
-rw-r--r--src/drivers/oxford/oxpcie/oxpcie_early.c89
8 files changed, 220 insertions, 0 deletions
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index f0bb966cf7..98f2079eea 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -22,6 +22,7 @@ source src/drivers/dec/Kconfig
source src/drivers/emulation/Kconfig
source src/drivers/generic/Kconfig
source src/drivers/i2c/Kconfig
+source src/drivers/oxford/Kconfig
source src/drivers/sil/Kconfig
source src/drivers/trident/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index 232f122c85..ae7a0989df 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -22,6 +22,7 @@ subdirs-y += dec
subdirs-y += emulation
subdirs-y += generic
subdirs-y += i2c
+subdirs-y += oxford
subdirs-y += sil
subdirs-y += trident
diff --git a/src/drivers/oxford/Kconfig b/src/drivers/oxford/Kconfig
new file mode 100644
index 0000000000..cd7c27ced0
--- /dev/null
+++ b/src/drivers/oxford/Kconfig
@@ -0,0 +1 @@
+source src/drivers/oxford/oxpcie/Kconfig
diff --git a/src/drivers/oxford/Makefile.inc b/src/drivers/oxford/Makefile.inc
new file mode 100644
index 0000000000..732face171
--- /dev/null
+++ b/src/drivers/oxford/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie
diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig
new file mode 100644
index 0000000000..899a1533b7
--- /dev/null
+++ b/src/drivers/oxford/oxpcie/Kconfig
@@ -0,0 +1,68 @@
+config DRIVERS_OXFORD_OXPCIE
+ bool "Oxford OXPCIe952"
+ default n
+ select HAVE_UART_MEMORY_MAPPED
+ help
+ Support for Oxford OXPCIe952 serial port PCIe cards.
+ Currently only devices with the vendor ID 0x1415 and device ID
+ 0xc158 will work.
+ NOTE: Right now you have to set the base address of your OXPCIe952
+ card to exactly the value that the device allocator would set them
+ later on, or serial console functionality will stop as soon as the
+ resource allocator assigns a new base address to the device.
+
+config OXFORD_OXPCIE_BRIDGE_BUS
+ hex "OXPCIe's PCIe bridge bus number"
+ default 0x0
+ depends on DRIVERS_OXFORD_OXPCIE
+ help
+ While coreboot is executing code from ROM, the coreboot resource
+ allocator has not been running yet. Hence PCI devices living behind
+ a bridge are not yet visible to the system. In order to use an
+ OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+ that controls the OXPCIe952 controller first.
+
+config OXFORD_OXPCIE_BRIDGE_DEVICE
+ hex "OXPCIe's PCIe bridge device number"
+ default 0x1c
+ depends on DRIVERS_OXFORD_OXPCIE
+ help
+ While coreboot is executing code from ROM, the coreboot resource
+ allocator has not been running yet. Hence PCI devices living behind
+ a bridge are not yet visible to the system. In order to use an
+ OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+ that controls the OXPCIe952 controller first.
+
+config OXFORD_OXPCIE_BRIDGE_FUNCTION
+ hex "OXPCIe's PCIe bridge function number"
+ default 0x2
+ depends on DRIVERS_OXFORD_OXPCIE
+ help
+ While coreboot is executing code from ROM, the coreboot resource
+ allocator has not been running yet. Hence PCI devices living behind
+ a bridge are not yet visible to the system. In order to use an
+ OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+ that controls the OXPCIe952 controller first.
+
+config OXFORD_OXPCIE_BRIDGE_SUBORDINATE
+ hex "OXPCIe's PCIe bridge subordinate bus"
+ default 0x3
+ depends on DRIVERS_OXFORD_OXPCIE
+ help
+ While coreboot is executing code from ROM, the coreboot resource
+ allocator has not been running yet. Hence PCI devices living behind
+ a bridge are not yet visible to the system. In order to use an
+ OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+ that controls the OXPCIe952 controller first.
+
+config OXFORD_OXPCIE_BASE_ADDRESS
+ hex "Base address for rom stage console"
+ default 0xe0400000
+ depends on DRIVERS_OXFORD_OXPCIE
+ help
+ While coreboot is executing code from ROM, the coreboot resource
+ allocator has not been running yet. Hence PCI devices living behind
+ a bridge are not yet visible to the system. In order to use an
+ OXPCIe952 based PCIe card, coreboot has to set up a temporary address
+ for the OXPCIe952 controller.
+
diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc
new file mode 100644
index 0000000000..7d3a26f509
--- /dev/null
+++ b/src/drivers/oxford/oxpcie/Makefile.inc
@@ -0,0 +1,3 @@
+driver-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c
+
+romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c
diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c
new file mode 100644
index 0000000000..94c5b64e66
--- /dev/null
+++ b/src/drivers/oxford/oxpcie/oxpcie.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <uart8250.h>
+
+static void oxford_oxpcie_enable(device_t dev)
+{
+ printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");
+
+ struct resource *res = find_resource(dev, 0x10);
+ if (!res) {
+ printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
+ return;
+ }
+
+ printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
+ (read32(res->base) >> 8), (read32(res->base) & 0xff));
+ printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
+ (read32(res->base + 4) & 3));
+}
+
+static struct device_operations oxford_oxpcie_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = oxford_oxpcie_enable,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver oxford_oxpcie_driver __pci_driver = {
+ .ops = &oxford_oxpcie_ops,
+ .vendor = 0x1415,
+ .device = 0xc158,
+};
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
new file mode 100644
index 0000000000..235c52c654
--- /dev/null
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <uart8250.h>
+#include <device/pci_def.h>
+
+#define PCIE_BRIDGE \
+ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \
+ CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \
+ CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
+
+#define OXPCIE_DEVICE \
+ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
+
+void oxford_init(void)
+{
+ u16 reg16;
+
+ /* First we reset the secondary bus */
+ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
+ reg16 |= (1 << 6); /* SRESET */
+ pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
+
+ /* Assume we don't have to wait here forever */
+
+ /* Read back and clear reset bit. */
+ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
+ reg16 &= ~(1 << 6); /* SRESET */
+ pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
+
+ /* Set up subordinate bus number */
+ pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00);
+ pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00);
+ pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS,
+ CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
+ pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS,
+ CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
+
+ /* Memory window for the OXPCIe952 card */
+ // XXX is the calculation of base and limit corect?
+ pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,
+ ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
+ ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
+
+ /* Enable memory access through bridge */
+ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MEMORY;
+ pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
+
+ // FIXME Add a timeout or this will hang forever if
+ // no device is in the slot.
+ u32 id = 0;
+ while ((id == 0) || (id == 0xffffffff))
+ id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
+
+ /* Setup base address on device */
+ pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0,
+ CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
+
+ /* Enable memory on device */
+ reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MEMORY;
+ pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16);
+
+ /* Now the UART initialization */
+ u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
+
+ uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));
+}
+