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-rw-r--r--src/drivers/intel/fsp1_1/cache_as_ram.inc46
-rw-r--r--src/drivers/intel/fsp1_1/car.c75
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/car.h11
3 files changed, 35 insertions, 97 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index f50641e3ae..493dbc8d04 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -31,11 +31,11 @@
* EBX, EDI, ESI, EBP, MM0, MM1
*
* Shift values to release MM2.
- * mm0 -> edi: BIST value
+ * mm0 -> ebx: BIST value
* mm1 -> mm0: low 32-bits of TSC value
* mm2 -> mm1: high 32-bits of TSC value
*/
- movd %mm0, %edi
+ movd %mm0, %ebx
movd %mm1, %eax
movd %eax, %mm0
movd %mm2, %eax
@@ -79,8 +79,8 @@ find_fsp_ret:
/*
* BIST value is zero
* eax: TempRamInitApi address
+ * ebx: BIST value
* ebp: FSP_INFO_HEADER address
- * edi: BIST value
* esi: Not used
* mm0: low 32-bits of TSC value
* mm1: high 32-bits of TSC value
@@ -90,13 +90,12 @@ find_fsp_ret:
jmp *%eax
CAR_init_done:
- addl $4, %esp
/*
* ebp: FSP_INFO_HEADER address
+ * ebx: BIST value
* ecx: Temp RAM base
* edx: Temp RAM top
- * edi: BIST value
* mm0: low 32-bits of TSC value
* mm1: high 32-bits of TSC value
*/
@@ -109,43 +108,42 @@ CAR_init_done:
/*
* ebp: FSP_INFO_HEADER address
+ * ebx: BIST value
* ecx: Temp RAM base
* edx: Temp RAM top
- * edi: BIST value
* esp: Top of stack in temp RAM
* mm0: low 32-bits of TSC value
* mm1: high 32-bits of TSC value
*/
- /* Create cache_as_ram_params on stack */
- pushl %edx /* bootloader CAR end */
- pushl %ecx /* bootloader CAR begin */
- pushl %ebp /* FSP_INFO_HEADER */
- pushl %edi /* bist */
- movd %mm1, %eax
- pushl %eax /* tsc[63:32] */
- movd %mm0, %eax
- pushl %eax /* tsc[31:0] */
- pushl %esp /* pointer to cache_as_ram_params */
-
- /* Save FSP_INFO_HEADER location in ebx */
- mov %ebp, %ebx
-
/* coreboot assumes stack/heap region will be zero */
cld
movl %ecx, %edi
neg %ecx
- /* Only clear up to current stack value. */
- add %esp, %ecx
+ /* Clear up to Temp Ram top. */
+ add %edx, %ecx
shrl $2, %ecx
xorl %eax, %eax
rep stosl
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the pushes below. */
+ andl $0xfffffff0, %esp
+ subl $4, %esp
+
+ /* Push BIST and initial timestamp on the stack */
+ pushl %ebx /* bist */
+ movd %mm1, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm0, %eax
+ pushl %eax /* tsc[31:0] */
+
before_romstage:
post_code(0x2A)
- /* Call cache_as_ram_main(struct cache_as_ram_params *) */
- call cache_as_ram_main
+ /* Call bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+ in cpu/intel/car/romstage.c */
+ call bootblock_c_entry_bist
movb $0x69, %ah
jmp .Lhlt
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 41a02f33b9..10f9524650 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -94,74 +94,25 @@ void platform_enter_postcar(void)
run_postcar_phase(&pcf);
}
-/* This is the romstage C entry for platforms without
- CONFIG_C_ENVIRONMENT_BOOTBLOCK */
-asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params)
-{
- int i;
- const int num_guards = 4;
- const u32 stack_guard = 0xdeadbeef;
- u32 *stack_base;
- u32 size;
-
- /* Size of unallocated CAR. */
- size = _car_region_end - _car_relocatable_data_end;
- size = ALIGN_DOWN(size, 16);
-
- stack_base = (u32 *)(_car_region_end - size);
-
- for (i = 0; i < num_guards; i++)
- stack_base[i] = stack_guard;
-
- /* Initialize timestamp book keeping only once. */
- timestamp_init(car_params->tsc);
-
- /* Call into pre-console init code then initialize console. */
- car_soc_pre_console_init();
- car_mainboard_pre_console_init();
- console_init();
-
- printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
-
- printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
- printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
-
- display_mtrrs();
-
- if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE
- || car_params->bootloader_car_end != (CONFIG_DCACHE_RAM_BASE
- + CONFIG_DCACHE_RAM_SIZE)) {
- printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
- CONFIG_DCACHE_RAM_BASE,
- CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
- (long)car_params->bootloader_car_start,
- (long)car_params->bootloader_car_end);
- }
-
- car_soc_post_console_init();
- car_mainboard_post_console_init();
-
- cache_as_ram_stage_main(car_params->fih);
-
- /* Check the stack. */
- for (i = 0; i < num_guards; i++) {
- if (stack_base[i] == stack_guard)
- continue;
- printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
- }
-
- /* we don't return here */
- platform_enter_postcar();
-}
-
-/* This is the entry for platforms with CONFIG_C_ENVIRONMENT_BOOTBLOCK
- called from cpu/intel/car/romstage.c */
+/* This is the romstage entry called from cpu/intel/car/romstage.c */
void mainboard_romstage_entry(unsigned long bist)
{
/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
* is still enabled. We can directly access work buffer here. */
struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
+ if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) {
+ /* Call into pre-console init code then initialize console. */
+ car_soc_pre_console_init();
+ car_mainboard_pre_console_init();
+ console_init();
+
+ display_mtrrs();
+
+ car_soc_post_console_init();
+ car_mainboard_post_console_init();
+ }
+
if (prog_locate(&fsp))
die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin");
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
index c05139231c..8d7a683672 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -20,17 +20,6 @@
#include <fsp/api.h>
#include <stdint.h>
-/* cache-as-ram support for FSP 1.1. */
-struct cache_as_ram_params {
- uint64_t tsc;
- uint32_t bist;
- FSP_INFO_HEADER *fih;
- uintptr_t bootloader_car_start;
- uintptr_t bootloader_car_end;
-};
-
-/* Entry points from the cache-as-ram assembly code. */
-asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params);
/* Per stage calls from the above two functions. The void * return from
* cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 11:33:34 +0000