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-rw-r--r--src/drivers/intel/fsp1_1/car.c4
-rw-r--r--src/drivers/intel/fsp1_1/raminit.c2
-rw-r--r--src/drivers/intel/fsp2_0/hob_verify.c4
3 files changed, 4 insertions, 6 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 7455d30047..8bb9f33d46 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -12,12 +12,10 @@
void fill_postcar_frame(struct postcar_frame *pcf)
{
- uintptr_t top_of_ram;
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations. */
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK);
}
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 2aec5db7cd..247df04fdd 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -138,7 +138,7 @@ void raminit(struct romstage_params *params)
}
/* Migrate CAR data */
- printk(BIOS_DEBUG, "%p: cbmem_top\n", cbmem_top());
+ printk(BIOS_DEBUG, "%lx: cbmem_top\n", cbmem_top());
if (!s3wake) {
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
fsp_reserved_bytes);
diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c
index ec526e850d..0726b60da3 100644
--- a/src/drivers/intel/fsp2_0/hob_verify.c
+++ b/src/drivers/intel/fsp2_0/hob_verify.c
@@ -43,8 +43,8 @@ void fsp_verify_memory_init_hobs(void)
die("Space between FSP reserved region and BIOS TOLUM!\n");
}
- if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) {
- printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n",
+ if (range_entry_end(&tolum) != cbmem_top()) {
+ printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %lx: cbmem_top\n",
range_entry_end(&tolum), cbmem_top());
die("Space between cbmem_top and BIOS TOLUM!\n");
}