diff options
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.inc | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 934ae670dc..16712133e9 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -29,11 +29,20 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ /* - * eax: BIST value - * mm0: low 32-bits of TSC value - * mm1: high 32-bits of TSC value + * Per FSP1.1 specs, following registers are preserved: + * EBX, EDI, ESI, EBP, MM0, MM1 + * + * Shift values to release MM2. + * mm0 -> edi: BIST value + * mm1 -> mm0: low 32-bits of TSC value + * mm2 -> mm1: high 32-bits of TSC value */ - movl %eax, %edi + movd %mm0, %edi + movd %mm1, %eax + movd %eax, %mm0 + movd %mm2, %eax + movd %eax, %mm1 + cache_as_ram: post_code(0x20) |