17 files changed, 300 insertions, 114 deletions

diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h
index db4c3aedbd..5408d9e0d5 100644
--- a/src/drivers/intel/dptf/chip.h
+++ b/src/drivers/intel/dptf/chip.h
@@ -4,7 +4,7 @@
 #define _DRIVERS_INTEL_DPTF_CHIP_H_
 
 #include <acpi/acpigen_dptf.h>
-#include <timer.h> /* for MSECS_PER_SEC */
+#include <timer.h>
 
 #define DPTF_PASSIVE(src, tgt, tmp, prd) \
 	{.source = DPTF_##src, .target = DPTF_##tgt, .temp = (tmp), .period = (prd)}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index c452f0b00d..23eadfa978 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -9,7 +9,7 @@
 #include <fsp/car.h>
 #include <fsp/util.h>
 #include <soc/intel/common/mma.h>
-#include <soc/pm.h>		/* chip_power_state */
+#include <soc/pm.h>
 
 struct romstage_params {
 	uint32_t fsp_version;
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index dd08d77e1e..4c468e5534 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -8,7 +8,7 @@
 #include <cpu/x86/smm.h>
 #include <fsp/romstage.h>
 #include <fsp/util.h>
-#include <lib.h> /* hexdump */
+#include <lib.h>
 #include <string.h>
 #include <timestamp.h>
 
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 14d97426c2..285bedf8b7 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -31,6 +31,13 @@ config PLATFORM_USES_FSP2_2
 
 if PLATFORM_USES_FSP2_0
 
+config PLATFORM_USES_FSP2_X86_32
+	bool
+	default y
+	help
+	  The FSP 2.0 runs in x86_32 protected mode.
+	  Once there's a x86_64 FSP this needs to default to n.
+
 config HAVE_INTEL_FSP_REPO
 	bool
 	help
@@ -173,16 +180,6 @@ config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
 	  This allows deployed systems to bump their version number
 	  with the same FSP which will trigger a retrain of the memory.
 
-config FSP_PEIM_TO_PEIM_INTERFACE
-	bool
-	select FSP_USES_MP_SERVICES_PPI
-	help
-	  This option allows SOC user to create specific PPI for Intel FSP
-	  usage, coreboot will provide required PPI structure definitions
-	  along with all APIs as per EFI specification. So far this feature
-	  is limited till EFI_PEI_MP_SERVICE_PPI and this option might be
-	  useful to add further PPI if required.
-
 config HAVE_FSP_LOGO_SUPPORT
 	bool
 	default n
@@ -271,9 +268,4 @@ config SOC_INTEL_COMMON_FSP_RESET
 	  Common code block to handle platform reset request raised by FSP. The FSP
 	  will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that
 	  a reset is required.
-
-if FSP_PEIM_TO_PEIM_INTERFACE
-source "src/drivers/intel/fsp2_0/ppi/Kconfig"
-endif
-
 endif
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index b518bec180..094308022a 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -95,7 +95,6 @@ ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),)
 CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH)
 endif
 
-# Include PPI directory of CONFIG_FSP_PEIM_TO_PEIM_INTERFACE is enable
-subdirs-$(CONFIG_FSP_PEIM_TO_PEIM_INTERFACE) += ppi
+subdirs-y += ppi
 
 endif
diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c
index a134fed065..4f9366657d 100644
--- a/src/drivers/intel/fsp2_0/header_display.c
+++ b/src/drivers/intel/fsp2_0/header_display.c
@@ -19,24 +19,24 @@ void fsp_print_header_info(const struct fsp_header *hdr)
 	printk(BIOS_SPEW, "Type: %s/%s\n",
 			(hdr->component_attribute & 1) ? "release" : "debug",
 			(hdr->component_attribute & 2) ? "official" : "test");
-	printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n",
-		hdr->image_id, hdr->image_base, hdr->image_size);
+	printk(BIOS_SPEW, "image ID: %s, base 0x%zx + 0x%zx\n",
+		hdr->image_id, (size_t)hdr->image_base, (size_t)hdr->image_size);
 	printk(BIOS_SPEW, "\tConfig region        0x%zx + 0x%zx\n",
-		hdr->cfg_region_offset, hdr->cfg_region_size);
+		(size_t)hdr->cfg_region_offset, (size_t)hdr->cfg_region_size);
 
 	if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) {
 		printk(BIOS_SPEW, "\tMemory init offset   0x%zx\n",
-						hdr->memory_init_entry_offset);
+		       (size_t)hdr->memory_init_entry_offset);
 	}
 
 	if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) {
 		printk(BIOS_SPEW, "\tSilicon init offset  0x%zx\n",
-						hdr->silicon_init_entry_offset);
+		       (size_t)hdr->silicon_init_entry_offset);
 		if (CONFIG(PLATFORM_USES_FSP2_2))
 			printk(BIOS_SPEW, "\tMultiPhaseSiInit offset  0x%zx\n",
-						hdr->multi_phase_si_init_entry_offset);
+			       (size_t)hdr->multi_phase_si_init_entry_offset);
 		printk(BIOS_SPEW, "\tNotify phase offset  0x%zx\n",
-						hdr->notify_phase_entry_offset);
+		       (size_t)hdr->notify_phase_entry_offset);
 	}
 
 }
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
index f237a378f1..aa9a435a75 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -4,6 +4,7 @@
 #define _FSP2_0_INFO_HEADER_H_
 
 #include <types.h>
+#include <commonlib/bsd/compiler.h>
 
 #define FSP_HDR_OFFSET			0x94
 #if CONFIG(PLATFORM_USES_FSP2_2)
@@ -16,24 +17,29 @@
 #define FSP_HDR_ATTRIB_FSPM		2
 #define FSP_HDR_ATTRIB_FSPS		3
 
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
 struct fsp_header {
 	uint32_t fsp_revision;
-	size_t image_size;
-	uintptr_t image_base;
+	uint32_t image_size;
+	uint32_t image_base;
 	uint16_t image_attribute;
 	uint8_t spec_version;
 	uint16_t component_attribute;
-	size_t cfg_region_offset;
-	size_t cfg_region_size;
-	size_t temp_ram_init_entry;
-	size_t temp_ram_exit_entry;
-	size_t notify_phase_entry_offset;
-	size_t memory_init_entry_offset;
-	size_t silicon_init_entry_offset;
-	size_t multi_phase_si_init_entry_offset;
+	uint32_t cfg_region_offset;
+	uint32_t cfg_region_size;
+	uint32_t temp_ram_init_entry;
+	uint32_t temp_ram_exit_entry;
+	uint32_t notify_phase_entry_offset;
+	uint32_t memory_init_entry_offset;
+	uint32_t silicon_init_entry_offset;
+	uint32_t multi_phase_si_init_entry_offset;
 	char image_id[sizeof(uint64_t) + 1];
 	uint8_t revision;
-};
+} __packed;
+#else
+#error You need to implement this struct for x86_64 FSP
+#endif
+
 
 enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
 
diff --git a/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h b/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h
index 836e996631..3c30063111 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h
@@ -11,10 +11,36 @@
 #include <efi/efi_datatype.h>
 #include <fsp/soc_binding.h>
 
-/*
- * SOC must call this function to get required EFI_PEI_MP_SERVICES_PPI
- * structure.
- */
-efi_pei_mp_services_ppi *mp_fill_ppi_services_data(void);
+/* SOC must call this function to get required EFI_PEI_MP_SERVICES_PPI structure */
+void *mp_fill_ppi_services_data(void);
+
+/* get the number of logical processors in the platform */
+efi_return_status_t mp_get_number_of_processors(efi_uintn_t *number_of_processors,
+	efi_uintn_t *number_of_enabled_processors);
+
+/* get processor info such as id, status */
+efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number,
+	efi_processor_information *processor_info_buffer);
+
+/* executes a caller provided function on all enabled APs */
+efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure,
+	efi_uintn_t timeout_usec, void *argument);
+
+/* executes a caller provided function on all enabled APs + BSP */
+efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure,
+	efi_uintn_t timeout_usec, void *argument);
+
+/* executes a caller provided function on specific AP */
+efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure,
+	efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument);
+
+/* get the processor instance */
+efi_return_status_t mp_identify_processor(efi_uintn_t *processor_number);
+
+/* for the APIs that are not supported/required */
+static inline efi_return_status_t mp_api_unsupported(void)
+{
+	return FSP_UNSUPPORTED;
+}
 
 #endif	/* MP_SERVICE_PPI_H */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h
index 979cff3b91..827c95d980 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/upd.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h
@@ -21,6 +21,7 @@ struct FSP_UPD_HEADER {
 	uint8_t                       Reserved[23];
 } __packed;
 
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
 struct FSPM_ARCH_UPD {
 	///
 	/// Revision of the structure. For FSP v2.0 value is 1.
@@ -31,12 +32,12 @@ struct FSPM_ARCH_UPD {
 	/// Pointer to the non-volatile storage (NVS) data buffer.
 	/// If it is NULL it indicates the NVS data is not available.
 	///
-	void                        *NvsBufferPtr;
+	uint32_t                      NvsBufferPtr;
 	///
 	/// Pointer to the temporary stack base address to be
 	/// consumed inside FspMemoryInit() API.
 	///
-	void                        *StackBase;
+	uint32_t                      StackBase;
 	///
 	/// Temporary stack size to be consumed inside
 	/// FspMemoryInit() API.
@@ -53,7 +54,11 @@ struct FSPM_ARCH_UPD {
 	uint32_t                      BootMode;
 	uint8_t                       Reserved1[8];
 } __packed;
+#else
+#error You need to implement this struct for x86_64 FSP
+#endif
 
+#endif
 struct FSPS_ARCH_UPD {
 	///
 	/// Revision of the structure. For FSP v2.2 value is 1.
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 92f3d9d960..f2fcec4061 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -87,7 +87,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
 	void *data;
 	size_t mrc_size;
 
-	arch_upd->NvsBufferPtr = NULL;
+	arch_upd->NvsBufferPtr = 0;
 
 	if (!CONFIG(CACHE_MRC_SETTINGS))
 		return;
@@ -101,7 +101,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
 		return;
 
 	/* MRC cache found */
-	arch_upd->NvsBufferPtr = data;
+	arch_upd->NvsBufferPtr = (uintptr_t)data;
 
 	printk(BIOS_SPEW, "MRC cache found, size %zx\n", mrc_size);
 }
@@ -142,7 +142,7 @@ static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd,
 				stack_end) != CB_SUCCESS)
 		return CB_ERR;
 
-	arch_upd->StackBase = (void *)stack_begin;
+	arch_upd->StackBase = stack_begin;
 	return CB_SUCCESS;
 }
 
@@ -159,7 +159,7 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
 	 * Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack.
 	 */
 	if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) {
-		arch_upd->StackBase = temp_ram;
+		arch_upd->StackBase = (uintptr_t)temp_ram;
 		arch_upd->StackSize = sizeof(temp_ram);
 	} else if (setup_fsp_stack_frame(arch_upd, memmap)) {
 		return CB_ERR;
@@ -237,7 +237,7 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 
 	fsp_version = fsp_memory_settings_version(hdr);
 
-	upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
+	upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
 
 	fsp_verify_upd_header_signature(upd->FspUpdHeader.Signature, FSPM_UPD_SIGNATURE);
 
@@ -289,12 +289,12 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 	post_code(POST_MEM_PREINIT_PREP_END);
 
 	/* Call FspMemoryInit */
-	fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
+	fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->memory_init_entry_offset);
 	fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);
 
 	post_code(POST_FSP_MEMORY_INIT);
 	timestamp_add_now(TS_FSP_MEMORY_INIT_START);
-	if (ENV_X86_64)
+	if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
 		status = protected_mode_call_2arg(fsp_raminit,
 						  (uintptr_t)&fspm_upd,
 						  (uintptr_t)fsp_get_hob_list_ptr());
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index 8a51c0bad7..cbccc6eacf 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -16,7 +16,7 @@ static void fsp_notify(enum fsp_notify_phase phase)
 	if (!fsps_hdr.notify_phase_entry_offset)
 		die("Notify_phase_entry_offset is zero!\n");
 
-	fspnotify = (void *) (fsps_hdr.image_base +
+	fspnotify = (void *) (uintptr_t)(fsps_hdr.image_base +
 			    fsps_hdr.notify_phase_entry_offset);
 	fsp_before_debug_notify(fspnotify, &notify_params);
 
@@ -31,7 +31,7 @@ static void fsp_notify(enum fsp_notify_phase phase)
 		post_code(POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE);
 	}
 
-	if (ENV_X86_64)
+	if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
 		ret = protected_mode_call_1arg(fspnotify, (uintptr_t)&notify_params);
 	else
 		ret = fspnotify(&notify_params);
diff --git a/src/drivers/intel/fsp2_0/ppi/Kconfig b/src/drivers/intel/fsp2_0/ppi/Kconfig
index 4f77a32cb2..7cbc87f7ab 100644
--- a/src/drivers/intel/fsp2_0/ppi/Kconfig
+++ b/src/drivers/intel/fsp2_0/ppi/Kconfig
@@ -1,11 +1,28 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-config FSP_USES_MP_SERVICES_PPI
+config MP_SERVICES_PPI
 	bool
 	default n
 	depends on SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
 	help
-	  This option allows SoC user to create MP service PPI for Intel
-	  FSP usage, coreboot will provide EFI_PEI_MP_SERVICES_PPI structure
-	  definitions along with all APIs as per EDK2 specification. Intel FSP
-	  will use this PPI to run CPU feature programming on APs.
+	  This option allows to create MP service PPI for Intel FSP usage.
+	  Intel FSP will use this PPI to run CPU feature programming on APs.
+
+config MP_SERVICES_PPI_V1
+	bool
+	default n
+	select MP_SERVICES_PPI
+	help
+	  This option provides EFI_PEI_MP_SERVICES_PPI structure definitions
+	  along with all APIs as per EDK2 specification.
+
+config MP_SERVICES_PPI_V2
+	bool
+	default n
+	select MP_SERVICES_PPI
+	help
+	  This option provides EDKII_PEI_MP_SERVICES2_PPI structure definitions
+	  along with all APIs as per EDK2 specification. MP services2 PPI is slight
+	  modification over MP services1 PPIs. A new API StartupAllCPUs have been
+	  added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
+	  parameter has been removed from all MP PPI APIs.
diff --git a/src/drivers/intel/fsp2_0/ppi/Makefile.inc b/src/drivers/intel/fsp2_0/ppi/Makefile.inc
index 8d8d990abb..8bda899ea9 100644
--- a/src/drivers/intel/fsp2_0/ppi/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/ppi/Makefile.inc
@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-ramstage-$(CONFIG_FSP_USES_MP_SERVICES_PPI) += mp_service_ppi.c
+ramstage-$(CONFIG_MP_SERVICES_PPI) += mp_service_ppi.c
+ramstage-$(CONFIG_MP_SERVICES_PPI_V1) += mp_service1.c
+ramstage-$(CONFIG_MP_SERVICES_PPI_V2) += mp_service2.c
diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service1.c b/src/drivers/intel/fsp2_0/ppi/mp_service1.c
new file mode 100644
index 0000000000..7d351e40f4
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/ppi/mp_service1.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+#include <fsp/ppi/mp_service_ppi.h>
+#include <Ppi/MpServices.h>
+
+typedef EFI_PEI_MP_SERVICES_PPI efi_pei_mp_services_ppi;
+
+static efi_return_status_t mps1_get_number_of_processors(const
+	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
+	efi_uintn_t *number_of_processors, efi_uintn_t *number_of_enabled_processors)
+{
+	return mp_get_number_of_processors(number_of_processors, number_of_enabled_processors);
+}
+
+static efi_return_status_t mps1_get_processor_info(const
+	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
+	efi_uintn_t processor_number,
+	efi_processor_information *processor_info_buffer)
+{
+	return mp_get_processor_info(processor_number, processor_info_buffer);
+}
+
+static efi_return_status_t mps1_startup_all_aps(const
+	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
+	efi_ap_procedure procedure, efi_boolean_t ignored3,
+	efi_uintn_t timeout_usec, void *argument)
+{
+	return mp_startup_all_aps(procedure, timeout_usec, argument);
+}
+
+static efi_return_status_t mps1_startup_this_ap(const
+	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
+	efi_ap_procedure procedure, efi_uintn_t processor_number,
+	efi_uintn_t timeout_usec, void *argument)
+{
+	return mp_startup_this_ap(procedure, processor_number, timeout_usec, argument);
+}
+
+static efi_return_status_t mps1_switch_bsp(const efi_pei_services **ignored1,
+	efi_pei_mp_services_ppi *ignored2, efi_uintn_t ignored3,
+	efi_boolean_t ignored4)
+{
+	return mp_api_unsupported();
+}
+
+static efi_return_status_t mps1_enable_disable_ap(const
+	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
+	efi_uintn_t ignored3, efi_boolean_t ignored4, efi_uint32_t *ignored5)
+{
+	return mp_api_unsupported();
+}
+
+static efi_return_status_t mps1_identify_processor(const
+	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
+	efi_uintn_t *processor_number)
+{
+	return mp_identify_processor(processor_number);
+}
+
+/* EDK2 UEFIPKG Open Source MP Service PPI to be installed */
+
+static efi_pei_mp_services_ppi mp_service1_ppi = {
+	mps1_get_number_of_processors,
+	mps1_get_processor_info,
+	mps1_startup_all_aps,
+	mps1_startup_this_ap,
+	mps1_switch_bsp,
+	mps1_enable_disable_ap,
+	mps1_identify_processor,
+};
+
+void *mp_fill_ppi_services_data(void)
+{
+	return (void *)&mp_service1_ppi;
+}
diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service2.c b/src/drivers/intel/fsp2_0/ppi/mp_service2.c
new file mode 100644
index 0000000000..8d27b16e77
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/ppi/mp_service2.c
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+#include <fsp/ppi/mp_service_ppi.h>
+#include <Ppi/MpServices2.h>
+
+typedef EDKII_PEI_MP_SERVICES2_PPI efi_pei_mp_services_ppi;
+
+static efi_return_status_t mps2_get_number_of_processors(
+	efi_pei_mp_services_ppi *ignored1,
+	efi_uintn_t *number_of_processors,
+	efi_uintn_t *number_of_enabled_processors)
+{
+	return mp_get_number_of_processors(number_of_processors, number_of_enabled_processors);
+}
+
+static efi_return_status_t mps2_get_processor_info(
+	efi_pei_mp_services_ppi *ignored1,
+	efi_uintn_t processor_number,
+	efi_processor_information *processor_info_buffer)
+{
+	return mp_get_processor_info(processor_number, processor_info_buffer);
+}
+
+static efi_return_status_t mps2_startup_all_aps(
+	efi_pei_mp_services_ppi *ignored1,
+	efi_ap_procedure procedure, efi_boolean_t ignored2,
+	efi_uintn_t timeout_usec, void *argument)
+{
+	return mp_startup_all_aps(procedure, timeout_usec, argument);
+}
+
+static efi_return_status_t mps2_startup_all_cpus(
+	efi_pei_mp_services_ppi *ignored1,
+	efi_ap_procedure procedure,
+	efi_uintn_t timeout_usec, void *argument)
+{
+	return mp_startup_all_cpus(procedure, timeout_usec, argument);
+}
+
+static efi_return_status_t mps2_startup_this_ap(
+	efi_pei_mp_services_ppi *ignored1,
+	efi_ap_procedure procedure, efi_uintn_t processor_number,
+	efi_uintn_t timeout_usec, void *argument)
+{
+	return mp_startup_this_ap(procedure, processor_number, timeout_usec, argument);
+}
+
+static efi_return_status_t mps2_switch_bsp(
+	efi_pei_mp_services_ppi *ignored1, efi_uintn_t ignored2,
+	efi_boolean_t ignored3)
+{
+	return mp_api_unsupported();
+}
+
+static efi_return_status_t mps2_enable_disable_ap(
+	efi_pei_mp_services_ppi *ignored1,
+	efi_uintn_t ignored2, efi_boolean_t ignored3, efi_uint32_t *ignored4)
+{
+	return mp_api_unsupported();
+}
+
+static efi_return_status_t mps2_identify_processor(
+	efi_pei_mp_services_ppi *ignored1,
+	efi_uintn_t *processor_number)
+{
+	return mp_identify_processor(processor_number);
+}
+
+/* EDK2 UEFIPKG Open Source MP Services 2 PPI to be installed */
+
+static efi_pei_mp_services_ppi mp_service2_ppi = {
+	mps2_get_number_of_processors,
+	mps2_get_processor_info,
+	mps2_startup_all_aps,
+	mps2_startup_this_ap,
+	mps2_switch_bsp,
+	mps2_enable_disable_ap,
+	mps2_identify_processor,
+	mps2_startup_all_cpus,
+};
+
+void *mp_fill_ppi_services_data(void)
+{
+	return (void *)&mp_service2_ppi;
+}
diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
index 03184e16ca..87056a5b7c 100644
--- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
+++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
@@ -12,9 +12,7 @@
 #define BSP_CPU_SLOT 0
 #define SINGLE_CHIP_PACKAGE 0
 
-static efi_return_status_t mp_get_number_of_processors(const
-	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
-	efi_uintn_t *number_of_processors,
+efi_return_status_t mp_get_number_of_processors(efi_uintn_t *number_of_processors,
 	efi_uintn_t *number_of_enabled_processors)
 {
 	if (number_of_processors == NULL || number_of_enabled_processors ==
@@ -27,9 +25,7 @@ static efi_return_status_t mp_get_number_of_processors(const
 	return FSP_SUCCESS;
 }
 
-static efi_return_status_t mp_get_processor_info(const
-	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
-	efi_uintn_t processor_number,
+efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number,
 	efi_processor_information *processor_info_buffer)
 {
 	unsigned int num_virt_cores, num_phys_cores;
@@ -62,9 +58,7 @@ static efi_return_status_t mp_get_processor_info(const
 	return FSP_SUCCESS;
 }
 
-static efi_return_status_t mp_startup_all_aps(const
-	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
-	efi_ap_procedure procedure, efi_boolean_t ignored3,
+efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure,
 	efi_uintn_t timeout_usec, void *argument)
 {
 	if (cpu_index() < 0)
@@ -82,14 +76,34 @@ static efi_return_status_t mp_startup_all_aps(const
 	return FSP_SUCCESS;
 }
 
-static efi_return_status_t mp_startup_this_ap(const
-	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
-	efi_ap_procedure procedure, efi_uintn_t processor_number,
+efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure,
 	efi_uintn_t timeout_usec, void *argument)
 {
 	if (cpu_index() < 0)
 		return FSP_DEVICE_ERROR;
 
+	if (procedure == NULL)
+		return FSP_INVALID_PARAMETER;
+
+	/* Run on BSP */
+	procedure(argument);
+
+	/* Run on APs */
+	if (mp_run_on_aps((void *)procedure, argument,
+			MP_RUN_ON_ALL_CPUS, timeout_usec)) {
+		printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
+		return FSP_NOT_STARTED;
+	}
+
+	return FSP_SUCCESS;
+}
+
+efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure,
+	efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument)
+{
+	if (cpu_index() < 0)
+		return FSP_DEVICE_ERROR;
+
 	if (processor_number > get_cpu_count())
 		return FSP_NOT_FOUND;
 
@@ -108,25 +122,7 @@ static efi_return_status_t mp_startup_this_ap(const
 	return FSP_SUCCESS;
 }
 
-static efi_return_status_t mp_switch_bsp(const efi_pei_services **ignored1,
-	efi_pei_mp_services_ppi *ignored2, efi_uintn_t ignored3,
-	efi_boolean_t ignored4)
-{
-	/* FSP don't need this API hence return unsupported */
-	return FSP_UNSUPPORTED;
-}
-
-static efi_return_status_t mp_enable_disable_ap(const
-	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
-	efi_uintn_t ignored3, efi_boolean_t ignored4, efi_uint32_t *ignored5)
-{
-	/* FSP don't need this API hence return unsupported */
-	return FSP_UNSUPPORTED;
-}
-
-static efi_return_status_t mp_identify_processor(const
-	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
-	efi_uintn_t *processor_number)
+efi_return_status_t mp_identify_processor(efi_uintn_t *processor_number)
 {
 	int index;
 
@@ -142,22 +138,3 @@ static efi_return_status_t mp_identify_processor(const
 
 	return FSP_SUCCESS;
 }
-
-/*
- * EDK2 UEFIPKG Open Source MP Service PPI to be installed
- */
-
-static efi_pei_mp_services_ppi mp_service_ppi = {
-	mp_get_number_of_processors,
-	mp_get_processor_info,
-	mp_startup_all_aps,
-	mp_startup_this_ap,
-	mp_switch_bsp,
-	mp_enable_disable_ap,
-	mp_identify_processor,
-};
-
-efi_pei_mp_services_ppi *mp_fill_ppi_services_data(void)
-{
-	return &mp_service_ppi;
-}
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 26ff59dbf2..8572b24901 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -86,7 +86,7 @@ static void do_silicon_init(struct fsp_header *hdr)
 	struct fsp_multi_phase_params multi_phase_params;
 	struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
 
-	supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
+	supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
 
 	fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE);
 
@@ -110,14 +110,14 @@ static void do_silicon_init(struct fsp_header *hdr)
 		logo_entry = soc_load_logo(upd);
 
 	/* Call SiliconInit */
-	silicon_init = (void *) (hdr->image_base +
+	silicon_init = (void *) (uintptr_t)(hdr->image_base +
 				 hdr->silicon_init_entry_offset);
 	fsp_debug_before_silicon_init(silicon_init, supd, upd);
 
 	timestamp_add_now(TS_FSP_SILICON_INIT_START);
 	post_code(POST_FSP_SILICON_INIT);
 
-	if (ENV_X86_64)
+	if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
 		status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd);
 	else
 		status = silicon_init(upd);
@@ -145,7 +145,7 @@ static void do_silicon_init(struct fsp_header *hdr)
 		return;
 
 	/* Call MultiPhaseSiInit */
-	multi_phase_si_init = (void *) (hdr->image_base +
+	multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base +
 			 hdr->multi_phase_si_init_entry_offset);
 
 	/* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */