diff options
Diffstat (limited to 'src/drivers/intel/fsp2_0')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 16 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/include/fsp/api.h | 4 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/silicon_init.c | 24 |
3 files changed, 36 insertions, 8 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3b03b6d1b7..ba93baa4de 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -274,4 +274,20 @@ config SOC_INTEL_COMMON_FSP_RESET Common code block to handle platform reset request raised by FSP. The FSP will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset is required. + +config FSPS_HAS_ARCH_UPD + bool + help + SoC users must select this Kconfig if the `FSPS_UPD` header has architecture + UPD structure as `FSPS_ARCH_UPD`. Typically, platform with FSP 2.2 specification + onwards has support for `FSPS_ARCH_UPD` section as part of `FSPS_UPD` structure. + But there are some exceptions as in TGL, JSL, XEON_SP FSP header doesn't have + support for FSPS_ARCH_UPD. + +config FSPS_USE_MULTI_PHASE_INIT + bool + help + SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and + execute FspMultiPhaseSiInit() API. + endif diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index a095b78b5f..68b84703ca 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -47,8 +47,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callbacks for SoC/Mainboard specific overrides */ void platform_fsp_multi_phase_init_cb(uint32_t phase_index); -/* Check if SoC sets EnableMultiPhaseSiliconInit UPD */ -int soc_fsp_multi_phase_init_is_enable(void); +/* Check if MultiPhase Si Init is enabled */ +bool fsp_is_multi_phase_init_enabled(void); /* * The following functions are used when FSP_PLATFORM_MEMORY_SETTINGS_VERSION * is employed allowing the mainboard and SoC to supply their own version diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index bf5230e90d..b3e60c25c3 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -29,11 +29,6 @@ void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index) /* Leave for the SoC/Mainboard to implement if necessary. */ } -int __weak soc_fsp_multi_phase_init_is_enable(void) -{ - return 1; -} - /* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2 * has multiple stages as below. */ @@ -77,6 +72,20 @@ static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint3 } } +bool fsp_is_multi_phase_init_enabled(void) +{ + return CONFIG(FSPS_USE_MULTI_PHASE_INIT) && + (fsps_hdr.multi_phase_si_init_entry_offset != 0); +} + +static void fsp_fill_common_arch_params(FSPS_UPD *supd) +{ +#if CONFIG(FSPS_HAS_ARCH_UPD) + FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; + s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled(); +#endif +} + static void do_silicon_init(struct fsp_header *hdr) { FSPS_UPD *upd, *supd; @@ -106,6 +115,9 @@ static void do_silicon_init(struct fsp_header *hdr) memcpy(upd, supd, hdr->cfg_region_size); + /* Fill common settings on behalf of chipset. */ + if (CONFIG(FSPS_HAS_ARCH_UPD)) + fsp_fill_common_arch_params(upd); /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); @@ -145,7 +157,7 @@ static void do_silicon_init(struct fsp_header *hdr) return; /* Check if SoC user would like to call Multi Phase Init */ - if (!soc_fsp_multi_phase_init_is_enable()) + if (!fsp_is_multi_phase_init_enabled()) return; /* Call MultiPhaseSiInit */ |