4 files changed, 2 insertions, 41 deletions
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 4088293e3f..e2f75eee51 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -28,7 +28,6 @@ romstage-y += fsp_util.c
 romstage-y += hob.c
 romstage-y += raminit.c
 romstage-y += romstage.c
-romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
 romstage-y += stack.c
 romstage-y += stage_cache.c
 romstage-$(CONFIG_MMA) += mma_core.c
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 1a5f9a8333..e1a9b9db6c 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -68,7 +68,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
 }
 
 /* Entry point taken when romstage is called after a separate verstage. */
-asmlinkage void *romstage_after_verstage(void)
+asmlinkage void *romstage_c_entry(void)
 {
 	/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
 	 * is still enabled. We can directly access work buffer here. */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
index 88dca9a0c5..5214d73b29 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -32,7 +32,7 @@ struct cache_as_ram_params {
 /* Entry points from the cache-as-ram assembly code. */
 asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
 asmlinkage void after_cache_as_ram(void *chipset_context);
-asmlinkage void *romstage_after_verstage(void);
+asmlinkage void *romstage_c_entry(void);
 /* Per stage calls from the above two functions. The void * return from
  * cache_as_ram_stage_main() is the stack pointer to use in RAM after
  * exiting cache-as-ram mode. */
diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S
deleted file mode 100644
index 2a3372f905..0000000000
--- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define LHLT_DELAY	0x50000		/* I/O delay between post codes on failure */
-
-.text
-.global car_stage_entry
-car_stage_entry:
-	call	romstage_after_verstage
-	#include "after_raminit.S"
-
-	movb	$0x69, %ah
-	jmp	.Lhlt
-
-.Lhlt:
-	xchg	%al, %ah
-#if IS_ENABLED(CONFIG_POST_IO)
-	outb	%al, $CONFIG_POST_IO_PORT
-#else
-	post_code(POST_DEAD_CODE)
-#endif
-	movl	$LHLT_DELAY, %ecx
-.Lhlt_Delay:
-	outb	%al, $0xED
-	loop	.Lhlt_Delay
-	jmp	.Lhlt