diff options
Diffstat (limited to 'src/drivers/intel/fsp1_1')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 6 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/ramstage.c | 14 |
2 files changed, 18 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index 5ce6aa8892..a9f6a8db22 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -21,6 +21,12 @@ #include <soc/intel/common/util.h> #include <stdint.h> +/* + * Load FSP from stage cache or CBFS. This allows SoCs to load FSP separately + * from calling silicon init. It might be required in cases where stage cache is + * no longer available by the point SoC calls into silicon init. + */ +void fsp_load(void); /* Perform Intel silicon init. */ void intel_silicon_init(void); void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup); diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index dd1abbeab7..7d9ff8edf0 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -185,11 +185,15 @@ static int fsp_find_and_relocate(struct prog *fsp) return 0; } -void intel_silicon_init(void) +void fsp_load(void) { + static int load_done; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); int is_s3_wakeup = acpi_is_wakeup_s3(); + if (load_done) + return; + if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsp); @@ -201,7 +205,13 @@ void intel_silicon_init(void) /* FSP_INFO_HEADER is set as the program entry. */ fsp_update_fih(prog_entry(&fsp)); - fsp_run_silicon_init(fsp_get_fih(), is_s3_wakeup); + load_done = 1; +} + +void intel_silicon_init(void) +{ + fsp_load(); + fsp_run_silicon_init(fsp_get_fih(), acpi_is_wakeup_s3()); } /* Initialize the UPD parameters for SiliconInit */ |