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Diffstat (limited to 'src/drivers/intel/fsp1_1/stage_cache.c')
-rw-r--r--src/drivers/intel/fsp1_1/stage_cache.c28
1 files changed, 0 insertions, 28 deletions
diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c
deleted file mode 100644
index ab0c1c0126..0000000000
--- a/src/drivers/intel/fsp1_1/stage_cache.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <stage_cache.h>
-
-void stage_cache_external_region(void **base, size_t *size)
-{
- if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
- printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
- *size = 0;
- }
-}