diff options
Diffstat (limited to 'src/drivers/intel/fsp1_0/fsp_util.c')
| -rw-r--r-- | src/drivers/intel/fsp1_0/fsp_util.c | 26 |
1 files changed, 7 insertions, 19 deletions
diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index d787c7beca..a7f3017230 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -25,7 +25,6 @@ #include <cpu/intel/microcode.h> #include <cf9_reset.h> -#ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ void *FspHobListPtr = NULL; FSP_INFO_HEADER *fsp_header_ptr = NULL; @@ -60,9 +59,6 @@ void FspNotify (u32 Phase) if (Status != 0) printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); } -#endif /* #ifndef __PRE_RAM__ */ - -#ifdef __PRE_RAM__ /* The FSP returns here after the fsp_early_init call */ static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) @@ -115,12 +111,10 @@ void __noreturn fsp_early_init (FSP_INFO_HEADER *fsp_ptr) /* Should never return. Control will continue from ContinuationFunc */ die("Uh Oh! FspInitApi returned"); } -#endif /* __PRE_RAM__ */ volatile u8 *find_fsp() { - -#ifdef __PRE_RAM__ +#if ENV_ROMSTAGE volatile register u8 *fsp_ptr asm ("eax"); /* Entry point for CAR assembly routine */ @@ -130,7 +124,7 @@ volatile u8 *find_fsp() ); #else volatile u8 *fsp_ptr; -#endif /* __PRE_RAM__ */ +#endif /* The FSP is stored in CBFS */ fsp_ptr = (u8 *) CONFIG_FSP_LOC; @@ -225,8 +219,6 @@ void *find_fsp_reserved_mem(void *hob_list_ptr) } #endif /* FSP_RESERVE_MEMORY_SIZE */ -#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ - void print_fsp_info(void) { if (fsp_header_ptr == NULL) @@ -249,12 +241,10 @@ void print_fsp_info(void) { (u8)(fsp_header_ptr->ImageRevision & 0xff)); } - -#if CONFIG(ENABLE_MRC_CACHE) /** * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM */ -int save_mrc_data(void *hob_start) +static int save_mrc_data(void *hob_start) { u32 *mrc_hob; u32 *mrc_hob_data; @@ -307,7 +297,6 @@ int save_mrc_data(void *hob_start) hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4); return (1); } -#endif /* CONFIG_ENABLE_MRC_CACHE */ static void find_fsp_hob_update_mrc(void *unused) { @@ -319,13 +308,13 @@ static void find_fsp_hob_update_mrc(void *unused) } else { /* 0x0000: Print all types */ print_hob_type_structure(0x000, FspHobListPtr); + } - #if CONFIG(ENABLE_MRC_CACHE) + if (CONFIG(ENABLE_MRC_CACHE)) { if (save_mrc_data(FspHobListPtr)) update_mrc_cache(NULL); else printk(BIOS_DEBUG,"Not updating MRC data in flash.\n"); - #endif } } @@ -356,11 +345,10 @@ static void fsp_finalize(void *unused) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); } + /* Set up for the ramstage FSP calls */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); /* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); |