diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 5 |
6 files changed, 30 insertions, 0 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index a7bce9e91b..53182726f1 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -269,6 +269,11 @@ clear_fixed_var_mtrr_out: */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 6ff0287186..d8465f4b2f 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -221,6 +221,11 @@ clear_fixed_var_mtrr_out: */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 03e0c2671c..9b7cad0cf9 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -97,6 +97,11 @@ clear_mtrrs: #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 6d88e7b8e5..acd0427c51 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -97,6 +97,11 @@ clear_mtrrs: #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 526d24520d..c270e44330 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -104,6 +104,11 @@ clear_mtrrs: #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index be00fe30dc..d6df4a90e9 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -97,6 +97,11 @@ clear_fixed_var_mtrr_out: */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr |