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-rw-r--r--src/cpu/amd/agesa/cache_as_ram.inc15
1 files changed, 7 insertions, 8 deletions
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 2a9beb8aa4..1258d154c3 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -28,7 +28,6 @@
/*
* XMM map:
- * xmm0: BIST
*/
.code32
@@ -36,6 +35,9 @@
cache_as_ram_setup:
+ /* Preserve BIST. */
+ movl %eax, %ebp
+
post_code(0xa0)
/* enable SSE2 128bit instructions */
@@ -45,11 +47,9 @@ cache_as_ram_setup:
orl $(3<<9), %eax
movl %eax, %cr4
- /* Save the BIST result */
- cvtsi2sd %ebp, %xmm0
-
post_code(0xa1)
+ /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
AMD_ENABLE_STACK
/* Align the stack. */
@@ -100,16 +100,15 @@ cache_as_ram_setup:
#endif
- call early_all_cores
+ /* Calling conventions preserve BIST in %ebp. */
- /* Restore the BIST result */
- cvtsd2si %xmm0, %edx
+ call early_all_cores
/* Must maintain 16-byte stack alignment here. */
pushl $0x0
pushl $0x0
pushl $0x0
- pushl %edx /* bist */
+ pushl %ebp
call romstage_main
/* Should never see this postcode */