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-rw-r--r--src/cpu/intel/car/cache_as_ram_ht.inc4
-rw-r--r--src/cpu/intel/fsp_model_206ax/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/haswell/romstage.c4
-rw-r--r--src/cpu/intel/model_2065x/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc4
-rw-r--r--src/cpu/x86/mtrr/mtrr.c4
7 files changed, 14 insertions, 14 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index fe1e29a5b3..fb653168b2 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -392,7 +392,7 @@ no_msr_11e:
movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
wrmsr
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
/* Enable caching and Speculative Reads for Flash ROM device. */
movl $MTRRphysBase_MSR(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
@@ -400,7 +400,7 @@ no_msr_11e:
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
rdmsr
- movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif
diff --git a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
index a8d7cc54cb..61fb1c2636 100644
--- a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
@@ -173,7 +173,7 @@ _clear_mtrrs_:
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
@@ -182,7 +182,7 @@ _clear_mtrrs_:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
- movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 35b51c5b59..edb2e80cdd 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -124,9 +124,9 @@ static void *setup_romstage_stack_after_car(void)
/* Cache the ROM as WP just below 4GiB. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid);
+ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid);
slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
num_mtrrs++;
/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index dce0e39dba..b791881d69 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -238,7 +238,7 @@ before_romstage:
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
@@ -247,7 +247,7 @@ before_romstage:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
- movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index b4119cc0b9..887d92bbe6 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -250,7 +250,7 @@ before_romstage:
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
@@ -259,7 +259,7 @@ before_romstage:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
- movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index ac3c66b734..baf4ae8617 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -186,14 +186,14 @@ clear_mtrrs:
movl $CPU_PHYSMASK_HI, %edx
wrmsr
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
/* Enable caching and Speculative Reads for Flash ROM device. */
movl $MTRRphysBase_MSR(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
- movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index d168978b54..dd404a887f 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -190,8 +190,8 @@ static struct memranges *get_physical_address_space(void)
* when CONFIG_CACHE_ROM is enabled. The ROM is assumed
* to be located at 4GiB - rom size. */
resource_t rom_base = RANGE_TO_PHYS_ADDR(
- RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE));
- memranges_insert(addr_space, rom_base, CONFIG_ROM_SIZE,
+ RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE));
+ memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
#endif