diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/allwinner/a10/clock.c | 9 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5250/cpu.c | 2 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/clock.c | 7 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/cpu.c | 4 | ||||
| -rw-r--r-- | src/cpu/x86/tsc/delay_tsc.c | 2 |
5 files changed, 7 insertions, 17 deletions
diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index 945dfd767b..f189aeae02 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -159,11 +159,6 @@ static const struct { { PLL1_CFG(20, 4, 1, 0), 1944 }, }; -static inline u32 div_ceil(u32 a, u32 b) -{ - return (a + b - 1) / b; -} - static void cpu_clk_src_switch(u32 clksel_bits) { u32 reg32; @@ -241,8 +236,8 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz) * will always be in spec, as long as AHB is in spec, although the max * AHB0 clock we can get is 125 MHz */ - axi = div_ceil(actual_mhz, 450); /* Max 450 MHz */ - ahb = div_ceil(actual_mhz/axi, 250); /* Max 250 MHz */ + axi = CEIL_DIV(actual_mhz, 450); /* Max 450 MHz */ + ahb = CEIL_DIV(actual_mhz/axi, 250); /* Max 250 MHz */ apb0 = 2; /* Max 150 MHz */ ahb_exp = log2_ceil(ahb); diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 2354be1352..9a44409402 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -140,7 +140,7 @@ static void cpu_enable(device_t dev) u32 lcdbase = get_fb_base_kb() * KiB; ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); + mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB)); exynos_displayport_init(dev, lcdbase, fb_size); diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 34d3fb58dc..7ecb717d75 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -40,11 +40,6 @@ static struct st_epll_con_val epll_div[] = { { 180633600, 0, 45, 3, 1, 10381 } }; -static inline unsigned long div_round_up(unsigned int n, unsigned int d) -{ - return (n + d - 1) / d; -} - /* exynos5: return pll clock frequency */ unsigned long get_pll_clk(int pllreg) { @@ -346,7 +341,7 @@ int clock_set_dwmci(enum periph_id peripheral) if (!sclk) { return -1; } - div = div_round_up(sclk, freq); + div = CEIL_DIV(sclk, freq); set_mmc_clk(device_index, div); return 0; } diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 5ff345eaa8..176a3f2595 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -140,7 +140,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, dcache_clean_invalidate_by_mva(lower, upper - lower); mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); - mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); + mmio_resource(dev, 1, lcdbase/KiB, CEIL_DIV(fb_size, KiB)); } static void tps65090_thru_ec_fet_disable(int index) @@ -160,7 +160,7 @@ static void cpu_enable(device_t dev) u32 lcdbase = get_fb_base_kb() * KiB; ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); + mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB)); /* * Disable LCD FETs before we do anything with the display. diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index b8f250394f..07a4053f41 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -78,7 +78,7 @@ static unsigned long long calibrate_tsc(void) if (end.lo <= CALIBRATE_DIVISOR) goto bad_ctc; - return (end.lo + CALIBRATE_DIVISOR -1)/CALIBRATE_DIVISOR; + return CEIL_DIV(end.lo, CALIBRATE_DIVISOR); } /* |