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-rw-r--r--src/cpu/amd/sc520/Config.lb6
-rw-r--r--src/cpu/amd/sc520/raminit.c17
-rw-r--r--src/cpu/amd/sc520/sc520.c191
3 files changed, 202 insertions, 12 deletions
diff --git a/src/cpu/amd/sc520/Config.lb b/src/cpu/amd/sc520/Config.lb
index b61acbc1ab..10bb9965a7 100644
--- a/src/cpu/amd/sc520/Config.lb
+++ b/src/cpu/amd/sc520/Config.lb
@@ -1,7 +1,3 @@
-uses CONFIG_CHIP_NAME
-
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
object sc520.o
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index aecf2b7723..273e0a47fc 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -214,13 +214,13 @@ setupsc520(void){
/* the 0x80 led should now be working*/
outb(0xaa, 0x80);
-
+#if 0
/* wtf are 680 leds ... */
par = (unsigned long *) 0xfffef0c4;
*par = 0x28000680;
/* well? */
outb(0x55, 0x80);
-
+#endif
/*; set the uart baud rate clocks to the normal 1.8432 MHz.*/
cp = (unsigned char *)0xfffefcc0;
@@ -232,7 +232,7 @@ setupsc520(void){
cp = (unsigned char *)0x0fffefd20;
*cp = 0x01;
- cp = (unsigned char *)0x0fffefd28;
+x cp = (unsigned char *)0x0fffefd28;
*cp = 0x0c;
cp = (unsigned char *)0x0fffefd29;
@@ -258,12 +258,12 @@ setupsc520(void){
outl(0xcfc, 0x2); /*set the memory access enable bit*/
OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
#endif
+ /* set up the PAR registers as they are on the MSM586SEG */
+ par = (unsigned long *) 0xfffef088;
#if 0
- /* set up the PAR registers as they are on the MSM586SEG */
- par = (unsigned long *) 0xfffef088;
*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
@@ -279,9 +279,12 @@ setupsc520(void){
*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
-// *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
-
+#else
+ par += 15;
#endif
+ *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
+
+
}
diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c
index a8e5b0baa2..7776e82cc8 100644
--- a/src/cpu/amd/sc520/sc520.c
+++ b/src/cpu/amd/sc520/sc520.c
@@ -1,7 +1,198 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
#include "chip.h"
+/*
+ * set up basic things ... PAR should NOT go here, as it might change with the mainboard.
+ */
+static void cpu_init(device_t dev)
+{
+ unsigned long *l = (unsigned long *) 0xfffef088;
+ int i;
+ for(i = 0; i < 16; i++, l++)
+ printk_err("Par%d: 0x%lx\n", i, *l);
+
+ printk_spew("SC520 random fixup ...\n");
+}
+
+
+
+static struct device_operations cpu_operations = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = cpu_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static struct pci_driver cpu_driver __pci_driver = {
+ .ops = &cpu_operations,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x3000
+};
+
+
+
+#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
+
+static void pci_domain_read_resources(device_t dev)
+{
+ struct resource *resource;
+ printk_spew("%s\n", __FUNCTION__);
+ /* Initialize the system wide io space constraints */
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
+ resource->limit = 0xffffUL;
+ resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+ /* Initialize the system wide memory resources constraints */
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
+ resource->limit = 0xffffffffULL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+ unsigned long basek, unsigned long sizek)
+{
+ struct resource *resource;
+ printk_spew("%s sizek 0x%x\n", __FUNCTION__, sizek);
+ if (!sizek) {
+ return;
+ }
+ resource = new_resource(dev, index);
+ resource->base = ((resource_t)basek) << 10;
+ resource->size = ((resource_t)sizek) << 10;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+ struct resource **best_p = gp;
+ struct resource *best;
+ best = *best_p;
+ if (!best || (best->base > new->base)) {
+ best = new;
+ }
+ *best_p = best;
+}
+
+static uint32_t find_pci_tolm(struct bus *bus)
+{
+ struct resource *min;
+ uint32_t tolm;
+ printk_spew("%s\n", __FUNCTION__);
+ min = 0;
+ search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+ tolm = 0xffffffffUL;
+ if (min && tolm > min->base) {
+ tolm = min->base;
+ }
+ printk_spew("%s returns 0x%x\n", __FUNCTION__, tolm);
+ return tolm;
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+ device_t mc_dev;
+ uint32_t pci_tolm;
+ printk_spew("%s\n", __FUNCTION__);
+ pci_tolm = find_pci_tolm(&dev->link[0]);
+ mc_dev = dev->link[0].children;
+ if (mc_dev) {
+ unsigned long tomk, tolmk;
+ // unsigned char rambits;
+ // int i;
+ int idx;
+#if 0
+ for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+ unsigned char reg;
+ reg = pci_read_config8(mc_dev, ramregs[i]);
+ /* these are ENDING addresses, not sizes.
+ * if there is memory in this slot, then reg will be > rambits.
+ * So we just take the max, that gives us total.
+ * We take the highest one to cover for once and future linuxbios
+ * bugs. We warn about bugs.
+ */
+ if (reg > rambits)
+ rambits = reg;
+ if (reg < rambits)
+ printk_err("ERROR! register 0x%x is not set!\n",
+ ramregs[i]);
+ }
+ printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+ tomk = rambits*8*1024;
+#endif
+ tomk = 32 * 1024;
+ /* Compute the top of Low memory */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does does not overlap the memory.
+ */
+ tolmk = tomk;
+ }
+ /* Report the memory regions */
+ idx = 10;
+ ram_resource(dev, idx++, 0, tolmk);
+ }
+ assign_resources(&dev->link[0]);
+}
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+ printk_spew("%s\n", __FUNCTION__);
+ max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+ return max;
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = enable_childrens_resources,
+ .init = 0,
+ .scan_bus = pci_domain_scan_bus,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+ printk_spew("cpu_bus_init\n");
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ printk_spew("%s\n", __FUNCTION__);
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ pci_set_method(dev);
+ }
+ else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
+}
+
struct chip_operations cpu_amd_sc520_ops = {
CHIP_NAME("AMD SC520")
+ .enable_dev = enable_dev,
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 12:52:22 +0000