7 files changed, 24 insertions, 30 deletions

diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
index 0cf5089fcc..5ef9295d92 100644
--- a/src/cpu/amd/agesa/family14/Kconfig
+++ b/src/cpu/amd/agesa/family14/Kconfig
@@ -40,9 +40,4 @@ config XIP_ROM_SIZE
 	hex
 	default 0x80000
 
-config HIGH_SCRATCH_MEMORY_SIZE
-	hex
-	# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
-	default 0x71000
-
 endif
diff --git a/src/cpu/amd/agesa/family15rl/Kconfig b/src/cpu/amd/agesa/family15rl/Kconfig
index 73b69764db..6524118991 100644
--- a/src/cpu/amd/agesa/family15rl/Kconfig
+++ b/src/cpu/amd/agesa/family15rl/Kconfig
@@ -41,9 +41,4 @@ config XIP_ROM_SIZE
 	hex
 	default 0x100000
 
-config HIGH_SCRATCH_MEMORY_SIZE
-	hex
-	# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
-	default 0xA1000
-
 endif # CPU_AMD_AGESA_FAMILY15_RL
diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
index e53a9883c4..8e274a3d99 100644
--- a/src/cpu/amd/agesa/family15tn/Kconfig
+++ b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -40,9 +40,4 @@ config XIP_ROM_SIZE
 	hex
 	default 0x100000
 
-config HIGH_SCRATCH_MEMORY_SIZE
-	hex
-	# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
-	default 0xA1000
-
 endif
diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
index 5f183dfa62..f7e87f7529 100644
--- a/src/cpu/amd/agesa/family16kb/Kconfig
+++ b/src/cpu/amd/agesa/family16kb/Kconfig
@@ -44,11 +44,6 @@ config XIP_ROM_SIZE
 	hex
 	default 0x100000
 
-config HIGH_SCRATCH_MEMORY_SIZE
-	hex
-	# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
-	default 0xA1000
-
 config FORCE_AM1_SOCKET_SUPPORT
 	bool
 	default n
diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c
index bfe8b2962d..b3af18c7ba 100644
--- a/src/cpu/amd/agesa/heapmanager.c
+++ b/src/cpu/amd/agesa/heapmanager.c
@@ -1,21 +1,25 @@
 
 #include "AGESA.h"
 #include "amdlib.h"
-#include <northbridge/amd/agesa/BiosCallOuts.h>
 #include "heapManager.h"
 
 #include <cbmem.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+
 #include <arch/acpi.h>
 #include <string.h>
 
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && (HIGH_MEMORY_SCRATCH < BIOS_HEAP_SIZE)
+#error Increase HIGH_MEMORY_SCRATCH allocation
+#endif
+
 UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader)
 {
 	UINT32 heap = BIOS_HEAP_START_ADDRESS;
 
 	if (acpi_is_wakeup_s3())
-		heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) +
-		 (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE);
-		  /* himem_heap_base + high_stack_size */
+		heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH);
 
 	return heap;
 }
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index d882bdf252..5e07d7a405 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -25,7 +25,6 @@
 #include <cpu/x86/cache.h>
 #include <cbmem.h>
 #include <string.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <halt.h>
 #include "s3_resume.h"
 
@@ -51,12 +50,12 @@ static void *backup_resume(void)
 
 static void move_stack_high_mem(void)
 {
-	void *high_stack;
+	void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK);
 
-	high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
-	memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR,
-		(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE));
+	/* TODO: Make the switch with empty stack instead. */
+	memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
 
+	/* TODO: We only switch stack on BSP. */
 	__asm__
 	    volatile ("add	%0, %%esp; add %0, %%ebp; invd"::"g"
 		      (high_stack - BSP_STACK_BASE_ADDR)
@@ -95,7 +94,6 @@ void prepare_for_resume(void)
 	post_code(0x62);
 	printk(BIOS_DEBUG, "Move CAR stack.\n");
 	move_stack_high_mem();
-	printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
 
 	post_code(0x63);
 	disable_cache_as_ram();
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index ce16f7dccf..97a2a21b91 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -26,4 +26,16 @@ void prepare_for_resume(void);
 void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
 const void *OemS3Saved_MTRR_Storage(void);
 
+#define BSP_STACK_BASE_ADDR		0x30000
+
+#if 1
+/* This covers node 0 only. */
+#define HIGH_ROMSTAGE_STACK_SIZE	(0x48000 - BSP_STACK_BASE_ADDR)
+#else
+/* This covers total of 8 nodes. */
+#define HIGH_ROMSTAGE_STACK_SIZE	(0xA0000 - BSP_STACK_BASE_ADDR)
+#endif
+
+#define HIGH_MEMORY_SCRATCH		0x30000
+
 #endif