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-rw-r--r--src/cpu/x86/smm/Makefile.inc1
-rw-r--r--src/cpu/x86/smm/smmrelocate.S6
2 files changed, 0 insertions, 7 deletions
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 1cd3622edc..239689e445 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -88,7 +88,6 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld
$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.S
ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual
endif
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 2283e7b8c9..f1972879ef 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -21,11 +21,6 @@
// Make sure no stage 2 code is included:
#define __PRE_RAM__
-/* On AMD's platforms we can set SMBASE by writing an MSR */
-#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 \
- && !CONFIG_CPU_AMD_AGESA_FAMILY15_TN \
- && !CONFIG_CPU_AMD_AGESA_FAMILY15_RL
-
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
// It's needed right now because we get our DEFAULT_PMBASE from
@@ -191,4 +186,3 @@ smm_relocate:
/* That's it. return */
rsm
smm_relocation_end:
-#endif