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-rw-r--r--src/cpu/amd/microcode/microcode.c2
-rw-r--r--src/cpu/x86/lapic/boot_cpu.c3
-rw-r--r--src/cpu/x86/smm/smmhandler.S6
3 files changed, 5 insertions, 6 deletions
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 29a550d529..e8ab17518b 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -127,7 +127,7 @@ static void apply_microcode_patch(const struct microcode *m)
UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);
/* read the patch_id again */
- msr = rdmsr(0x8b);
+ msr = rdmsr(IA32_BIOS_SIGN_ID);
new_patch_id = msr.lo;
UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id,
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 7ba21fe90c..4654086114 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -13,13 +13,14 @@
#include <smp/node.h>
#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic_def.h>
#if IS_ENABLED(CONFIG_SMP)
int boot_cpu(void)
{
int bsp;
msr_t msr;
- msr = rdmsr(0x1b);
+ msr = rdmsr(LAPIC_BASE_MSR);
bsp = !!(msr.lo & (1 << 8));
return bsp;
}
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 98d67d3c3c..0989e891e2 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -21,7 +21,7 @@
* to 64k if we can though.
*/
-#define LAPIC_BASE_MSR 0x1b
+#include <cpu/x86/lapic_def.h>
/*
* +--------------------------------+ 0xaffff
@@ -49,8 +49,6 @@
*
*/
-#define LAPIC_ID 0xfee00020
-
/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG
* at which smm_handler_start lives. At the moment the handler
* lives right at 0xa0000, so the offset is 0.
@@ -134,7 +132,7 @@ untampered_lapic:
movw %ax, %gs
/* Get this CPU's LAPIC ID */
- movl $LAPIC_ID, %esi
+ movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi
movl (%esi), %ecx
shr $24, %ecx