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-rw-r--r--src/cpu/intel/haswell/romstage.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index c6162dcc84..136f098e71 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -182,11 +182,6 @@ void romstage_common(const struct romstage_params *params)
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
- /* Ensure the EC is in the right mode for recovery */
- google_chromeec_early_init();
-#endif
-
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);