3 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c
index 69e08ca7f4..3ef5606d27 100644
--- a/src/cpu/allwinner/a10/twi.c
+++ b/src/cpu/allwinner/a10/twi.c
@@ -14,9 +14,9 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * Setup helpers for Two Wire Interface (TWI) (I²C) Allwinner CPUs
+ * Setup helpers for Two Wire Interface (TWI) (I2C) Allwinner CPUs
  *
- * Only functionality for I²C master is provided.
+ * Only functionality for I2C master is provided.
  * Largely based on the uboot-sunxi code.
  */
 
@@ -63,7 +63,7 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
 
 	configure_clock(twi, speed_hz);
 
-	/* Enable the I²C bus */
+	/* Enable the I2C bus */
 	write32(&twi->ctl, TWI_CTL_BUS_EN);
 	/* Issue soft reset */
 	write32(&twi->reset, 1);
diff --git a/src/cpu/allwinner/a10/twi.h b/src/cpu/allwinner/a10/twi.h
index a8ebdf345d..1a3341958a 100644
--- a/src/cpu/allwinner/a10/twi.h
+++ b/src/cpu/allwinner/a10/twi.h
@@ -13,7 +13,7 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * Definitions Two Wire Interface (TWI) (I²C) Allwinner CPUs
+ * Definitions Two Wire Interface (TWI) (I2C) Allwinner CPUs
  */
 
 #ifndef CPU_ALLWINNER_A10_TWI_H
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c
index 2699d9256a..7c127b3fb0 100644
--- a/src/cpu/intel/slot_1/l2_cache.c
+++ b/src/cpu/intel/slot_1/l2_cache.c
@@ -339,7 +339,7 @@ int test_l2_address_alias(u32 address1, u32 address2,
 
 /* Calculates the L2 cache size.
  *
- * Reference: Intel(R) 64 and IA-32 Architectures Software Developer�s Manual
+ * Reference: Intel(R) 64 and IA-32 Architectures Software Developer's Manual
  *            Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172.
  *
  */