diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 1 |
3 files changed, 1 insertions, 3 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index ddbffbbc60..e09e74b6c2 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -17,7 +17,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#include <cbmem.h> /* The full cache-as-ram size includes the cache-as-ram portion from coreboot * and the space used by the reference code. These 2 values combined should diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9932a508e5..9c08aa16ba 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -28,7 +28,7 @@ #include <arch/stages.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <cbfs.h> +#include <cbmem.h> #include <romstage_handoff.h> #include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 6fa3eb82b5..269fbeffc7 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -17,7 +17,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#include <cbmem.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |