diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/samsung/exynos5420/clk.h | 11 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/clock.c | 65 |
2 files changed, 36 insertions, 40 deletions
diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index b98a67384b..3d60b28009 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -35,9 +35,13 @@ enum periph_id; #define SPLL 7 enum pll_src_bit { - EXYNOS_SRC_MPLL = 6, - EXYNOS_SRC_EPLL, - EXYNOS_SRC_VPLL, + EXYNOS_SRC_CPLL = 1, + EXYNOS_SRC_DPLL = 2, + EXYNOS_SRC_MPLL = 3, + EXYNOS_SRC_SPLL = 4, + EXYNOS_SRC_IPLL = 5, + EXYNOS_SRC_EPLL = 6, + EXYNOS_SRC_RPLL = 7, }; /* * @@ -46,7 +50,6 @@ enum pll_src_bit { */ struct clk_bit_info { s8 src_bit; /* offset in register to clock source field */ - s8 n_src_bits; /* number of bits in 'src_bit' field */ s8 div_bit; s8 prediv_bit; }; diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index fd15486090..6e4701a826 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -30,39 +30,35 @@ /* src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { - {0, 4, 0, -1}, - {4, 4, 4, -1}, - {8, 4, 8, -1}, - {12, 4, 12, -1}, - {0, 4, 0, 8}, - {4, 4, 16, 24}, - {8, 4, 0, 8}, - {12, 4, 16, 24}, - {-1, -1, -1, -1}, - {16, 4, 0, 8}, /* PERIPH_ID_SROMC */ - {20, 4, 16, 24}, - {24, 4, 0, 8}, - {0, 4, 0, 4}, - {4, 4, 12, 16}, - {-1, 4, -1, -1}, - {-1, 4, -1, -1}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, /* PERIPH_ID_I2S1 */ - {24, 1, 20, -1}, /* PERIPH_ID_SATA */ + {0, 0, -1}, + {4, 4, -1}, + {8, 8, -1}, + {12, 12, -1}, + {0, 0, 8}, + {4, 16, 24}, + {8, 0, 8}, + {12, 16, 24}, + {-1, -1, -1}, + {16, 0, 8}, /* PERIPH_ID_SROMC */ + {20, 16, 24}, + {24, 0, 8}, + {0, 0, 4}, + {4, 12, 16}, + {-1, -1, -1}, + {-1, -1, -1}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, }; /* Epll Clock division values to achive different frequency output */ @@ -221,9 +217,6 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) case EXYNOS_SRC_EPLL: sclk = get_pll_clk(EPLL); break; - case EXYNOS_SRC_VPLL: - sclk = get_pll_clk(VPLL); - break; default: return 0; } |