6 files changed, 4 insertions, 85 deletions
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 9a11b06e4d..1f6d1a22b9 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -19,10 +19,6 @@ ramstage-y += acpi.c
 
 smm-y += finalize.c
 
-romstage-y += stage_cache.c
-ramstage-y += stage_cache.c
-postcar-y += stage_cache.c
-
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
 
 cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index eab2dd5c50..2f3584a67e 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -80,16 +80,9 @@ void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
 #endif
 
-/*
- * Region of SMM space is reserved for multipurpose use. It falls below
- * the IED region and above the SMM handler.
- */
-#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
-#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE)
-
 /* Sanity check config options. */
-#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE)
-# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE"
+#if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE)
+# error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE"
 #endif
 #if (CONFIG_SMM_TSEG_SIZE < 0x800000)
 # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c
deleted file mode 100644
index ab8ac979c1..0000000000
--- a/src/cpu/intel/model_2065x/stage_cache.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stage_cache.h>
-#include <cpu/intel/smm/gen1/smi.h>
-#include "model_2065x.h"
-
-void stage_cache_external_region(void **base, size_t *size)
-{
-	/*
-	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
-	 * The top of RAM is defined to be the TSEG base address.
-	 */
-	*size = RESERVED_SMM_SIZE;
-	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
-			 + RESERVED_SMM_OFFSET);
-}
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index f5de8c38fa..e723d74d78 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -24,10 +24,6 @@ smm-y += tsc_freq.c
 
 smm-y += finalize.c
 
-romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
 
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index c0d2434fe6..2dc929345d 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -81,17 +81,9 @@
 #define PSS_LATENCY_TRANSITION		10
 #define PSS_LATENCY_BUSMASTER		10
 
-/*
- * Region of SMM space is reserved for multipurpose use. It falls below
- * the IED region and above the SMM handler.
- */
-#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
-#define RESERVED_SMM_OFFSET \
-	(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
-
 /* Sanity check config options. */
-#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
-# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
+#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
+# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
 #endif
 #if (CONFIG_SMM_TSEG_SIZE < 0x800000)
 # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c
deleted file mode 100644
index 26dc5e03f9..0000000000
--- a/src/cpu/intel/model_206ax/stage_cache.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stage_cache.h>
-#include "model_206ax.h"
-
-void stage_cache_external_region(void **base, size_t *size)
-{
-	/*
-	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
-	 * The top of RAM is defined to be the TSEG base address.
-	 */
-	*size = RESERVED_SMM_SIZE;
-	*base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET);
-}